IC-MSB Datasheet, PDF (17/29 Pages) IC-Haus GmbH – SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER

iC-MSB^SAFETY, iC-MSB2
SIN/COS SIGNAL CONDITIONER WITH 1Vpp DRIVER
TEST MODE
Rev D2, Page 17/29
iC-MSB switches to test mode when a voltage greater
than VTMon is applied to pin ERR (precondition:
TMODE(0) = 1). In response iC-MSB transmits its con-
figuration settings as current-modulated data using er-
ror signal I/O pin ERR either directly from the RAM
(for TMEM = 1) or after re-reading the EEPROM (for
TMEM = 0).
TMEM
0
1
Adr 0x18, bit 7
EEPROM contents
iC-MSB RAM contents
Table 15: Test Mode Memory Selection
Should the voltage at the ERR pin fall below
VTMoff test mode is terminated and data transmission
aborted.
The clock rate for the data output is determined by
ENFAST. Two clock rates can be selected: 780 ns for
ENFAST = 1 or 3.125 µs for ENFAST = 0 (see Electri-
cal Characteristics, D08, for clock frequency and toler-
ances).
Data is output in Manchester code via two clock pulses
per bit. To this end the lowside current source switches
between a Z state (OFF = 0 mA) and an L state (ON =
2 mA).
The bit information lies in the direction of the current
source switch:
Zero bit: change of state Z → L (OFF to ON)
One bit: Change of state L → Z (ON to OFF)
Transmission consists of a start bit (a one bit), 8 data
bits and a pause interval in Z state (the timing is iden-
tical with an EEPROM access via the I²C interface).
Example: byte value = 1000 1010
Transmission including the start bit: 1 1000 1010
In Manchester code: LZ LZZL ZLZL LZZL LZZL
Decoding of the data stream:
When test mode is quit with TMODE > 0, then iC-
MSB again reads out its configuration from the EEP-
ROM, accessible at the device ID filed to DEVID(6:0)
of adr 0x00. In TMODE = 0x00 the EEPROM is read
completely; in all other cases only the address range
0x00 to 0x21 is read to keep the configuration time
for device testing short. When test mode is quit with
TMODE = 0x00 iC-MSB continues operation without
any interruption.
TMODE
Code
00
01
10
11
Adr 0x15, bit 7:6
Function during test
mode
Normal operation
TMEM = 0:
Transmission of
EEPROM data, address
range 0x1B-0x7F
TMEM = 1:
Transmission of RAM
data, address range
0x3B-0x43
Normal operation
Transmission of
EEPROM data, address
range 0x0-0x7F
Function following test
mode
Normal operation
Repeated read out of
EEPROM
Repeated read out of
EEPROM
Repeated read out of
EEPROM
Table 16: Test Mode Functions
VP
VP
C21
100nF
7
VP
U22-S
AD8029
VN
4
C22
100nF
8
VP
U23-S
LM393
GND
4
U23-B
VP LM393
6_-
7
5₊
JP4
ERR
DATA_ON
M22
IRLML6401
R26
100k
R28
51k
M21
2N7002
VP
R23
2K
D21
LL4148
R27
100k
R21
475k
R22
365k
8
U21
5
LM285
4
VDD
C23
100nF
R24
470
C24
100pF
U22-A
2_-
+ ³
AD8029
NDIS
8
VP
U23-A
LM393
6
2_-
3₊
C25
100nF
max. 5V
VDD
C26
100nF
R25
2k
1
DATA_OUT
dra_mq1d_error_s c hem
Figure 1: Example circuit for the decoding and con-
version of the current-modulated signals
to logic levels.
ZZZZZZ LZ LZ ZL ZL ZL LZ ZL LZ ZL ZZZZZZ
Pause 1 1 0 0 0 1 0 1 0 Pause