HY64UD16162M Datasheet, PDF (9/11 Pages) Hynix Semiconductor – 1M x 16 bit Low Low Power 1T/1C Pseudo SRAM

AVOID TIMING
HY64UD16162M Series
Hynix 1T/1C SRAM has a timing which is not supported at read operation. If your system has multiple
invalid address signal shorter than tRC during over 10us at read operation which showed in abnormal
timing, Hynix 1T/1C SRAM needs a normal read timing at least during 10us which showed in avoidable
timing(1) or toggle the /CS1 to high(≥tRC) one time at least which showed in avoidable timing(2)
ABNORMAL TIMING
/CS1
/WE
ADD
< tRC
AVOIDABLE TIMING(1)
/CS1
/WE
ADD
AVOIDABLE TIMING(2)
/CS1
/WE
ADD
< tRC
≥ 10us
≥ 10us
≥ tRC
≥ 10us
≥ tRC
Revision 1.7
9
March. 2002