HY64UD16162M Datasheet, PDF (1/11 Pages) Hynix Semiconductor – 1M x 16 bit Low Low Power 1T/1C Pseudo SRAM

HY64UD16162M Series
Document Title
1M x 16 bit Low Low Power 1T/1C Pseudo SRAM
Revision history
Revision No. History
Draft Date Remark
1.0
Initial
Jan. 04. ’ 01 Preliminary
1.1
Revised
Jul. 03. ’ 01 Preliminary
- Change Pin Connection
- Improve tOE from 45ns to 30ns
- Correct State Diagram
1.2
Revised
Jul.18. ’ 01 Preliminary
- Correct Package Dimension
- Change Absolute Maximum Ratings
1.3
Revised
Oct. 07. ‘ 01 Preliminary
- DC Electrical Characteristics ( IDPD,ICC1)
- State Diagram
- Power Up Sequence
- Deep Power Down Sequence
- Read/Write Cycle Note
1.4
Revised
Nov. 14. ’ 01 Preliminary
- DC Electrical Characteristics ( ICC1: 3mA - > 5mA)
1.5
Revised
Dec. 20. ‘ 01 Preliminary
- Improve Standby Current ISB1 from 100uA to 80uA
- Add 70ns Part
- Power Up Sequence
1.6
Revised
Feb. 27. ‘ 02 Preliminary
- Improve ISB1@70ns 100uA to 85uA
- Improve ISB1@85ns 80uA to 75uA
- Improve ICC2@70ns 30mA to 25mA
- Improve ICC2@85ns 30mA to 20mA
- Improve Ambient Temperature C/E to E/I
(0°C~85°C/-25°C~85°C → -25°C~85°C/-40°C~85°C)
- Improve Maximum Absolute Ratings
(Vdd : -0.3V to 3.3V → -0.3V to 3.6V)
- Improve tOE@85ns 30ns to 20ns
1.7
Revised
Mar. 11. ‘ 02 Final
- Pin Description
- Power Up & Deep Power Down Exit Sequence
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not
assume any responsibility for use of circuits described. No patent licenses are implied.
Revision 1.7
1
March. 2002