HY64UD16162M Datasheet, PDF (6/11 Pages) Hynix Semiconductor – 1M x 16 bit Low Low Power 1T/1C Pseudo SRAM

HY64UD16162M Series
Power-Up Sequence
1. Supply power.
2. Maintain stable power for longer than 200µs.
Deep Power Down Entry Sequence
1. Keep CS2 low state.
Deep power down mode is maintained while CS2 is low state.
Deep Power Down Exit Sequence
1. Keep CS2 high state.
2. Maintain stable power for longer than 200µs.
STATE DIAGRAM
PPoowweerrOOnn
WWaaiitt 220000µµss
CS2=VIH
/ CS1=VIL, CS2=VIH,
/UB&/LB≠VIH
SSttaannddbbyy
MMooddee
AAccttiivvee
CS2=VIH, /CS1=VIH
or /UB,/LB=VIH
CS2=VIL
CS2=VIL
DDeeeepp PPoowweerr
DDoowwnn MMooddee
Deep Power Down
Entry Sequence
STANDBY MODE CHARACTERISTICS
Mode
Memory Cell Data
Standby
Valid
Deep Power Down
Invalid
Revision 1.7
March. 2002
Standby Current[µA]
85 / 70ns
75 / 85ns
2
Wait Time[µs]
0
200
6