HY64UD16162M Datasheet, PDF (7/11 Pages) Hynix Semiconductor – 1M x 16 bit Low Low Power 1T/1C Pseudo SRAM

TIMING DIAGRAM
READ CYCLE 1 ( Note 1, 4 )
ADD
/CS1
CS2
Vih
/UB, /LB
/OE
Data Out
High-Z
tRC
tAA
tACS
tBA
tOE
tOLZ(3)
tBLZ(3)
tCLZ(3)
READ CYCLE 2 ( Note 1, 2, 4 )( CS2=Vih )
tRC
ADD
tAA
tOH
Data Out
Previous Data
READ CYCLE 3 ( Note 1, 2, 4 )( CS2=Vih )
/CS1
/UB, /LB
Data Out
High-Z
tACS
tCLZ(3)
HY64UD16162M Series
tOH
tCHZ(3)
tBHZ(3)
tOHZ(3)
Data Valid
tOH
Data Valid
tCHZ(3)
Data Valid
Notes :
1. Read Cycle occurs whenever a high on the /WE and /OE is low, while /UB and/or /LB and /CS1 and CS2 are in active status.
2. /OE = VIL
3. tCHZ, tBHZ and tOHZ are defined as the time at which the outputs achieve the high impedance state and tOLZ,tBLZ and tCLZ
are defined as the time at which the outputs achieve the low impedance state.
These are not referenced to output voltage levels.
4. /CS1 in high for the standby, low for active.
/UB and /LB in high for the standby, low for active.
Revision 1.7
7
March. 2002