GMS81C1404 Datasheet, PDF (74/93 Pages) Hynix Semiconductor – 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C1404/GMS81C1408
21. POWER FAIL PROCESSOR
The GMS81C1404 and GMS81C1408 has an on-chip
power fail detection circuitry to immunize against power
noise. A configuration register, PFDR, can enable (if clear/
programmed) or disable (if set) the Power-fail Detect cir-
cuitry. If V_DD falls below 2.5~3.5V(2.0~3.0V) range for
longer than 50 nS, the Power fail situation may reset MCU
according to PFS bit of PFDR. And power fail detect level
is selectable by mask option. On the other hand, in the
OTP, power fail detect level is decided by setting the bit
PFDLEVEL of CONFIG register when program the OTP.
As below PFDR register is not implemented on the in-cir-
cuit emulator, user can not experiment with it. Therefore,
after final development of user program, this function may
be experimented.
Note: Power fail detect level is decided by mask option
checking the bit PFDLEVEL of MASK ORDER
SHEET (refer to MASK ORDER SHEET)
In thc case of OTP, Power fail detect level is decid-
ed by setting the bit PFDLEVEL of CONFIG register
(refer to Figure 22-1 .
PFDR
Power Fail Detector Register
-
-
-
-
Reserved
-
PFDIS PFDM
PFS
ADDRESS : EFH
RESET VALUE : -----100
Power Fail Status
0 : Normal Operate
1 : This bit force to “1” when
Power fail was detected
Operation Mode
0 : System Clock Freeze during power fail
1 : MCU will be reset during power fail
Disable Flag
0 : Power fail detection enable
1 : Power fail detection disable
Figure 21-1 Power Fail Detector Register
RESET VECTOR
PFS =1
YES
NO
RAM CLEAR
INITIALIZE RAM DATA
INITIALIZE ALL PORTS
INITIALIZE REGISTERS
Skip the
initial routine
FUNTION
EXECUTION
Figure 21-2 Example S/W of RESET by Power fail
72
June. 2001 Ver 1.2