GMS81C1404 Datasheet, PDF (67/93 Pages) Hynix Semiconductor – 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C1404/GMS81C1408
19. Power Saving Mode
For applications where power consumption is a critical
factor, device provides two kinds of power saving func-
tions, STOP mode and Wake-up Timer mode.
The power saving function is activated by execution of
STOP instruction after setting the corresponding status
(WAKEUP) of CKCTLR.
Table 19-1 shows the status of each Power Saving Mode.
Peripheral
RAM
Control Registers
I/O Ports
CPU
Timer0, Timer2
Oscillation
Prescaler
Entering Condition
[WAKEUP]
Release Sources
STOP
Retain
Retain
Retain
Stop
Stop
Stop
Stop
0
RESET, RCWDT, INT0~3,
EC0~1, SPI
Wake-up Timer
Retain
Retain
Retain
Stop
Operation
Oscillation
÷ 2048 only
1
RESET, RCWDT, INT0~3,
EC0~1, SPI, TIMER0, TIMER2
Table 19-1 Power Saving Mode
19.1 Stop Mode
In the Stop mode, the on-chip oscillator is stopped. With
the clock frozen, all functions are stopped, but the on-chip
RAM and Control registers are held. The port pins out the
values held by their respective port data register, port di-
rection registers. Oscillator stops and the systems internal
operations are all held up.
• The states of the RAM, registers, and latches valid
immediately before the system is put in the STOP
state are all held.
• The program counter stop the address of the
instruction to be executed after the instruction
“STOP” which starts the STOP operating mode.
The Stop mode is activated by execution of STOP in-
struction after clearing the bit WAKEUP of CKCTLR
to “0”. (This register should be written by byte opera-
tion. If this register is set by bit manipulation instruc-
tion, for example “set1” or “clr1” instruction, it may be
undesired operation)
In the Stop mode of operation, V_DD can be reduced to min-
imize power consumption. Care must be taken, however,
to ensure that V_DD is not reduced before the Stop mode is
invoked, and that V_DD is restored to its normal operating
level, before the Stop mode is terminated.
The reset should not be activated before V_DD is restored to
its normal operating level, and must be held active long
enough to allow the oscillator to restart and stabilize.
Note: After STOP instruction, at least two or more NOP in-
struction should be written
Ex)
LDM
CKCTLR,#0000_1110B
STOP
NOP
NOP
In the STOP operation, the dissipation of the power asso-
ciated with the oscillator and the internal hardware is low-
ered; however, the power dissipation associated with the
pin interface (depending on the external circuitry and pro-
gram) is not directly determined by the hardware operation
of the STOP feature. This point should be little current
flows when the input level is stable at the power voltage
level (V_DD/V_SS); however, when the input level gets high-
er than the power voltage level (by approximately 0.3 to
0.5V), a current begins to flow. Therefore, if cutting off the
output transistor at an I/O port puts the pin signal into the
high-impedance state, a current flow across the ports input
transistor, requiring to fix the level by pull-up or other
means.
June. 2001 Ver 1.2
65