GMS81C1404 Datasheet, PDF (29/93 Pages) Hynix Semiconductor – 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C1404/GMS81C1408
9.3 Data Memory
Figure 9-7 shows the internal Data Memory space availa-
ble. Data Memory is divided into two groups, a user RAM
(including Stack) and control registers.
0000H
00BFH
00C0H
00FFH
USER
MEMORY
(including STACK)
CONTROL
REGISTERS
PAGE0
Figure 9-7 Data Memory Map
User Memory
The GMS81C1404 and GMS81C1408 has 192 × 8 bits for
the user memory (RAM).
Control Registers
The control registers are used by the CPU and Peripheral
function blocks for controlling the desired operation of the
device. Therefore these registers contain control and status
bits for the interrupt system, the timer/ counters, analog to
digital converters and I/O ports. The control registers are in
address range of 0C0_H to 0FF_H.
Note that unoccupied addresses may not be implemented
on the chip. Read accesses to these addresses will in gen-
eral return random data, and write accesses will have an in-
determinate effect.
More detailed informations of each register are explained
in each peripheral section.
Note: Write only registers can not be accessed by bit ma-
nipulation instruction. Do not use read-modify-write
instruction. Use byte manipulation instruction.
Example; To write at CKCTLR
LDM CKCTLR,#09H ;Divide ratio ÷16
Address Symbol R/W
RESET
Value
Addressing
mode
0C0H
RA
R/W Undefined byte, bit¹
0C1H
RAIO
R/W 0000_0000 _byte²
0C2H
RB
R/W Undefined _{byte, bit}
0C3H
RBIO
R/W 00000000
byte
0C4H
RC
R/W Undefined _{byte, bit}
0C5H
RCIO R/W -000_0--- _byte
0C6H
RD
R/W Undefined _{byte, bit}
0C7H RDIO
W ----_-000 _byte
0CAH RAFUNC W 0000_0000 _byte
0CBH RBFUNC W 0000_0000 _byte
0CCH PUPSEL W ----_0000 _byte
0CDH RDFUNC W ----_--00 _byte
0D0H
TM0
R/W --00_0000 byte, bit
0D1H
T0
R 0000_0000 byte
0D1H TDR0
W 1111_1111 byte
0D1H CDR0
R 0000_0000 byte
0D2H
TM1
R/W 0000_0000 byte, bit
0D3H TDR1
W 1111_1111 byte
0D3H T1PPR W 1111_1111 byte
0D4H
T1
R 0000_0000 byte
0D4H CDR1
R 0000_0000 byte
0D4H T1PDR R/W 0000_0000 byte, bit
0D5H PWM0HR W ----_0000 byte
0D6H
TM2
R/W --00_0000 byte, bit
0D7H
T2
R 0000_0000 byte
0D7H TDR2
W 1111_1111 byte
0D7H CDR2
R 0000_0000 byte
0D8H
TM3
R/W 0000_0000 byte, bit
0D9H TDR3
W 1111_1111 byte
0D9H T3PPR W 1111_1111 byte
0DAH
T3
R 0000_0000 byte
0DAH CDR3
R 0000_0000 byte
0DAH T3PDR R/W 0000_0000 byte, bit
0DBH PWM1HR W ----_0000 byte
0DEH
0E0H
0E1H
BUR
SIOM
SIOR
W 1111_1111 byte
R/W 0000_0001 byte, bit
R/W Undefined byte, bit
0E2H
0E3H
0E4H
0E5H
0E6H
0EAH
0EBH
0ECH
0ECH
0EDH
0EDH
0EFH
IENH
IENL
IRQH
IRQL
IEDS
ADCM
ADCR
BITR
CKCTLR
WDTR
WDTR
PFDR
R/W 0000_0000 byte, bit
R/W 0000_---- byte, bit
R/W 0000_0000 byte, bit
R/W 0000_---- byte, bit
R/W 0000_0000 byte, bit
R/W --00_0001 byte, bit
R Undefined byte
R 0000_0000 byte
W -001_0111 byte
R 0000_0000 byte
W 0111_1111 byte
R/W ----_-100 byte, bit
Table 9-1 Control Registers
June. 2001 Ver 1.2
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