GMS81C1404 Datasheet, PDF (56/93 Pages) Hynix Semiconductor – 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C1404/GMS81C1408
16. ANALOG TO DIGITAL CONVERTER
The analog-to-digital converter (A/D) allows conversion
of an analog input signal to a corresponding 8-bit digital
value. The A/D module has eight analog inputs, which are
multiplexed into one sample and hold. The output of the
sample and hold is the input into the converter, which gen-
erates the result via successive approximation.
The analog reference voltage is selected to V_DD or AVref
by setting of the bit AVREFS in RBFUNC register. If ex-
ternal analog reference AVref is selected, the bit ANSEL0
should not be set to “1”, because this pin is used to an an-
alog reference of A/D converter.
The A/D module has two registers which are the control
register ADCM and A/D result register ADCR. The
ADCM register, shown in Figure 16-2 , controls the oper-
ation of the A/D converter module. The port pins can be
configure as analog inputs or digital I/O.
To use analog inputs, each port is assigned analog input
port by setting the bit ANSEL[7:0] in RAFUNC register.
And selected the corresponding channel to be converted by
setting ADS[2:0].
The processing of conversion is start when the start bit
ADST is set to “1”. After one cycle, it is cleared by hard-
ware. The register ADCR contains the results of the A/D
conversion. When the conversion is completed, the result
is loaded into the ADCR, the A/D conversion status bit
ADSF is set to “1”, and the A/D interrupt flag ADIF is set.
The block diagram of the A/D module is shown in Figure
16-1 . The A/D status bit ADSF is set automatically when
A/D conversion is completed, cleared when A/D conver-
sion is in process. The conversion time takes maximum 10
uS (at fxin=8 MHz).
ADS[2:0]
RA7/AN7
RA6/AN6
RA5/AN5
RA4/AN4
RA3/AN3
RA2/AN2
RA1/AN1
RB0/AN0/AVref
111
ANSEL7
110
ANSEL6
101
ANSEL5
100
ANSEL4
011
ANSEL3
010
ANSEL2
001
ANSEL1
000
ANSEL0 (RAFUNC.0)
Sample & Hold
S/H
Resistor
Ladder
Circuit
A/D Result Register
ADCR(8-bit)
ADDRESS : EBH
RESET VALUE : Undefined
Successive
Approximation
Circuit
A D IF
A/D Interrupt
VDD Pin
1
0
ADEN
AVREFS (RBFUNC.0)
Figure 16-1 A/D Converter Block Diagram
54
June. 2001 Ver 1.2