GMS81C1404 Datasheet, PDF (71/93 Pages) Hynix Semiconductor – 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C1404/GMS81C1408
Note: After STOP instruction, at least two or more NOP in-
struction should be written
Ex)
LDM TDR0,#0FFH
LDM TM0,#0001_1011B
LDM CKCTLR,#0100_1110B
STOP
NOP
NOP
In addition, the clock source of timer0 and timer2 should
be selected to 2048 devided ratio. Otherwise, the wake-up
function can not work. And the timer0 and timer2 can be
operated as 16-bit timer with timer1 and timer3(refer to
timer function). The period of wake-up function is varied
by setting the timer data register0, TDR0 or timer data
register2, TDR2.
Release the Wake-up Timer mode
The exit from Wake-up Timer mode is hardware reset,
Timer0(Timer2) overflow or external interrupt. Reset re-
defines all the Control registers but does not change the on-
chip RAM. External interrupts and Timer0(Timer2) over-
flow allow both on-chip RAM and Control registers to re-
tain their values.
If I-flag = 1, the normal interrupt response takes place. If I-
flag = 0, the chip will resume execution starting with the
instruction following the STOP instruction. It will not vec-
tor to interrupt service routine.(refer to Figure 19-1 )
When exit from Wake-up Timer mode by external inter-
rupt or timer0(Timer2) overflow, the oscillation stabilizing
time is not required to normal operation. Because this
mode do not stop the on-chip oscillator shown as Figure
19-6 .
Oscillator
(X_IN pin)
CPU
Clock
Interrupt
Request
STOP Instruction
Execution
Normal Operation
Wake-up Timer Mode
(stop the CPU clock)
Normal Operation
Do not need Stabilizing Time
Figure 19-6 Wake-up Timer Mode Releasing by External Interrupt or Timer0(Timer2) Interrupt
19.4 Minimizing Current Consumption
The Stop mode is designed to reduce power consumption.
To minimize current drawn during Stop mode, the user
should turn-off output drivers that are sourcing or sinking
current, if it is practical.
Note: In the STOP operation, the power dissipation asso-
ciated with the oscillator and the internal hardware
is lowered; however, the power dissipation associat-
ed with the pin interface (depending on the external
circuitry and program) is not directly determined by
the hardware operation of the STOP feature. This
point should be little current flows when the input
level is stable at the power voltage level (V_DD/V_SS);
however, when the input level becomes higher than
the power voltage level (by approximately 0.3V), a
current begins to flow. Therefore, if cutting off the
output transistor at an I/O port puts the pin signal
into the high-impedance state, a current flow across
the ports input transistor, requiring it to fix the level
by pull-up or other means.
It should be set properly that current flow through port
doesn't exist.
First conseider the setting to input mode. Be sure that there
is no current flow after considering its relationship with
external circuit. In input mode, the pin impedance viewing
from external MCU is very high that the current doesn’t
flow.
But input voltage level should be V_SS or V_DD. Be careful
that if unspecified voltage, i.e. if uncertain voltage level
(not V_SSor V_DD) is applied to input pin, there can be little
current (max. 1mA at around 2V) flow.
If it is not appropriate to set as an input mode, then set to
output mode considering there is no current flow. Setting
to High or Low is decided considering its relationship with
external circuit. For example, if there is external pull-up re-
sistor then it is set to output mode, i.e. to High, and if there
is external pull-down register, it is set to low.
June. 2001 Ver 1.2
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