GMS81C1404 Datasheet, PDF (64/93 Pages) Hynix Semiconductor – 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C1404/GMS81C1408
17.4 External Interrupt
The external interrupt on INT0, INT1, INT2 and INT3 pins
are edge triggered depending on the edge selection register
IEDS (address 0E6_H) as shown in Figure 17-6 .
The edge detection of external interrupt has three transition
activated mode: rising edge, falling edge, and both edge.
INT0 pin
INT1 pin
INT0IF
INT0 INTERRUPT
INT1IF
INT1 INTERRUPT
INT2 pin
INT2IF
INT2 INTERRUPT
INT3 pin
INT3IF
INT3 INTERRUPT
IEDS
[0E6_H]
Figure 17-6 External Interrupt Block Diagram
Example: To use as an INT0 and INT2
:
:
;**** Set port as an input port RB2,RD0
LDM RBIO,#1111_1011B
LDM RDIO,#1111_1110B
;
;**** Set port as an interrupt port
LDM RBFUNC,#04H
LDM RDFUNC,#01H
;
;**** Set Falling-edge Detection
LDM IEDS,#0001_0001B
:
:
:
Response Time
The INT0, INT1,INT2 and INT3 edge are latched into
INT0IF, INT1IF, INT2IF and INT3IF at every machine
cycle. The values are not actually polled by the circuitry
until the next machine cycle. If a request is active and con-
ditions are right for it to be acknowledged, a hardware sub-
routine call to the requested service routine will be the next
instruction to be executed. The DIV itself takes twelve cy-
cles. Thus, a minimum of twelve complete machine cycles
elapse between activation of an external interrupt request
and the beginning of execution of the first instruction of
the service routine.
Ext. Interrupt Edge Selection
Register
W WW W
IESR
ADDRESS : 0E6_H
RESET VALUE : 00000000
W WW W
INT2 edge select
00 : Int. disable
01 : falling
10 : rising
11 : both
INT3 edge select
00 : Int. disable
01 : falling
10 : rising
11 : both
INT0 edge select
00 : Int. disable
01 : falling
10 : rising
11 : both
INT1 edge select
00 : Int. disable
01 : falling
10 : rising
11 : both
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June. 2001 Ver 1.2