GMS81C1404 Datasheet, PDF (48/93 Pages) Hynix Semiconductor – 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS81C1404/GMS81C1408
timer register T0 (T1) increases and matches TDR0
(TDR1).
This timer interrupt in capture mode is very useful when
the pulse width of captured signal is more wider than the
maximum period of Timer.
For example, in Figure 13-8 , the pulse width of captured
signal is wider than the timer data value (FF_H) over 2
times. When external interrupt is occurred, the captured
value (13_H) is more little than wanted value. It can be ob-
tained correct value by counting the number of timer over-
flow occurrence.
Timer/Counter still does the above, but with the added fea-
ture that a edge transition at external input INTx pin causes
the current value in the Timer x register (T0,T1), to be cap-
tured into registers CDRx (CDR0, CDR1), respectively.
After captured, Timer x register is cleared and restarts by
hardware.
It has three transition modes: “falling edge”, “rising edge”,
“both edge” which are selected by interrupt edge selection
register IEDS (Refer to External interrupt section). In ad-
dition, the transition at INTx pin generate an interrupt.
Note: The CDRx, TDRx and Tx are in same address. In
the capture mode, reading operation is read the
CDRx, not Tx because path is opened to the CDRx,
and TDRx is only for writing operation.
TM0
TM1
EC0
fxin
INT0
INT1
-
-
CAP0
-
-
1
POL
16BIT PWME
X
0
0
Edge Detector
T0CK[2:0]
T0CK2 T0CK1 T0CK0
X
X
X
CAP1 T1CK1 T1CK0
1
X
X
T0CN
X
T0ST
X
ADDRESS : D0H
RESET VALUE : --000000
T1CN T1ST
ADDRESS : D2H
RESET VALUE : 00000000
X
X
T0ST
0 : Stop
1 : Clear and Start
÷2
÷4
÷8
÷ 32
÷ 128
÷ 512
÷ 2048
MUX
1
CLEAR
T0 (8-bit)
T0CN
CAPTURE
CDR0 (8-bit)
T0IF
COMPARATOR
TDR0 (8-bit)
TIMER 0
INTERRUPT
IEDS[1:0]
INT0IF
T0ST
0 : Stop
1 : Clear and Start
INT 0
INTERRUPT
÷1
1
÷2
MUX
÷8
T1CK[1:0]
T1CN
T1 (8-bit)
CLEAR
T1IF
COMPARATOR
TIMER 1
INTERRUPT
IEDS[3:2]
CAPTURE
CDR1 (8-bit) TDR1 (8-bit)
INT1IF
INT 1
INTERRUPT
Figure 13-6 8-bit Capture Mode
46
June. 2001 Ver 1.2