HMT451V7MFR8C Datasheet, PDF (7/67 Pages) Hynix Semiconductor – DDR3 SDRAM VLP Registered DIMM Based on 4Gb M-die

Symbol
DQS[17:0]
DQS[17:0]
TDQS[17:9]
TDQS[17:9]
SA[2:0]
SDA
SCL
EVENT
V_DDSPD
RESET
Par_In
Err_Out
TEST
Type
I/O
I/O
OUT
IN
I/O
IN
OUT
(open
drain)
Supply
IN
IN
OUT
(open
drain)
Polarity
Function
Positive
Edge
Positive line of the differential data strobe for input and output data.
Negative
Edge
Negative line of the differential data strobe for input and output data.
TDQS/TDQS is applicable for X8 DRAMs only. When enabled via Mode Register A11=1 in
MR1,DRAM will enable the same termination resistance function on TDQS/TDQS that is
applied to DQS/DQS. When disabled via mode register A11=0 in MR1, DM/TDQS will
provide the data mask function and TDQS is not used. X4 DRAMs must disable the TDQS
function via mode register A11=0 in MR1
—
These signals are tied at the system planar to either V_SS or V_DDSPD to configure the
serial SPD EEPROM address range.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor
—
must be connected from the SDA bus line to V_DDSPD on the system planar to act as a
pullup.
—
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be con-
nected from the SCL bus time to V_DDSPD on the system planar to act as a pullup.
Active Low
This signal indicates that a thermal event has been detected in the thermal sensing
device.The system should guarantee the electrical level requirement is met for the
EVENT pin on TS/SPD part.
No pull-up resister is provided on DIMM.
Serial EEPROM positive power supply wired to a separate power pin at the connector
which supports from 3.0 Volt to 3.6 Volt (nominal 3.3V) operation.
The RESET pin is connected to the RESET pin on the register and to the RESET pin on
the DRAM.
Parity bit for the Address and Control bus. (“1 “: Odd, “0 “: Even)
Parity error detected on the Address and Control bus. A resistor may be connected from
Err_Out bus line to V_DD on the system planar to act as a pull up.
Used by memory bus analysis tools (unused (NC) on memory DIMMs)
Rev. 1.0 / Aug. 2012
7