HMT451V7MFR8C Datasheet, PDF (30/67 Pages) Hynix Semiconductor – DDR3 SDRAM VLP Registered DIMM Based on 4Gb M-die

Single-ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL or DQSU
Symbol
VSEH
VSEL
Notes:
Parameter
Single-ended high level for strobes
Single-ended high level for Ck, CK
Single-ended low level for strobes
Single-ended low level for CK, CK
DDR3-800, 1066, 1333, & 1600
Min
(VDD / 2) + 0.175
(VDD /2) + 0.175
Note 3
Note 3
Max
Note 3
Note 3
(VDD / 2) = 0.175
(VDD / 2) = 0.175
Unit Notes
V 1,2
V 1,2
V 1,2
V 1,2
1. For CK, CK use VIH/VIL (ac) of ADD/CMD; for strobes (DQS, DQS, DQSL, DQSL, DQSU, DQSU) use VIH/VIL (ac)
of DQs.
2. VIH (ac)/VIL (ac) for DQs is based on VREFDQ; VIH (ac)/VIL (ac) for ADD/CMD is based on VREFCA; if a reduced
ac-high or ac-low level is used for a signal group, then the reduced level applies also here.
3. These values are not defined; however, the single-ended signals Ck, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU
need to be within the respective limits (VIH (dc) max, VIL (dc) min) for single-ended signals as well as the limita-
tions for overshoot and undershoot. Refer to "Overshoot and Undershoot Specifications" on page 37.
Rev. 1.0 / Aug. 2012
30