HMT451V7MFR8C Datasheet, PDF (21/67 Pages) Hynix Semiconductor – DDR3 SDRAM VLP Registered DIMM Based on 4Gb M-die

16GB, 2Gx72 Module(4Rank of x8) - page3
S0_n
S1_n
S2_n
S3_n
BA[N:0]
A[N:0]
RAS_n
CAS_n
WE_n
CKE0
CKE1
ODT0
ODT1
CK0_t
CK0_c
CK1_t
CK1_c
1:2
R
E
G
I
S
T
E
R
/
P
L
L
120 Ω
120 Ω
RS0_n → CS1_n: SDRAMs D[17:9]
RS1_n → CS0_n: SDRAMs D[8:0]
RS2_n → CS1_n: SDRAMs D[35:27]
RS3_n → CS0_n: SDRAMs D[26:18]
RBA[N:0]A → BA[N:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
RBA[N:0]B → BA[N:0]: SDRAMs D[7:4], D[16:13], U[25:22], U[34:31]
RA[N:0]A → A[N:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
RA[N:0]B → A[N:0]: SDRAMs D[7:4], D[16:13], U[25:22], U[34:31]
RRASA_n → RAS_n: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
RRASB_n → RAS_n: SDRAMs D[7:4], D[16:13], U[25:22], U[34:31]
RCASA_n → CAS_n: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
RCASB_n → CAS_n: SDRAMs D[7:4], D[16:13], U[25:22], U[34:31]
RWEA_n → WE_n: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
RWEB_n → WE_n: SDRAMs D[7:4], D[16:13], U[25:22], U[34:31]
RCKE0A → CKE1: SDRAMs D[12:9], D17, D[30:27], D35
RCKE0B → CKE1: SDRAMs D[16:13], D[34:31]
RCKE1A → CKE0: SDRAMs D[3:0], D8, D[21:18], D26
RCKE1B → CKE0: SDRAMs D[7:4], D[25:22]
RODT0A → ODT1: SDRAMs D[12:9], D17
RODT0B → ODT1: SDRAMs D[16:13]
RODT1A → ODT1: SDRAMs D[30:27], D35
RODT1B → ODT1: SDRAMs D[34:31]
PCK0A_t → CK_t: SDRAMs D[3:0], D[12:8], D17
PCK0B_t → CK_t: SDRAMs D[7:4], D[16:13]
PCK1A_t → CK_t: SDRAMs D[21:18], D[30:26], D35
PCK1B_t → CK_t: SDRAMs D[25:22], D[34:31]
PCK0A_c → CK_c: SDRAMs D[3:0], D[12:8], D17
PCK0B_c → CK_c: SDRAMs D[7:4], D[16:13]
PCK1A_c → CK_c: SDRAMs D[21:18], D[30:26], D35
PCK1B_c → CK_c: SDRAMs D[25:22], D[34:31]
PAR_IN
RESET_n
Err_Out_n
RST_n
RESET_n: SDRAMs D[35:0]
Rev. 1.0 / Aug. 2012
21