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HMT451V7MFR8C Datasheet, PDF (18/67 Pages) Hynix Semiconductor – DDR3 SDRAM VLP Registered DIMM Based on 4Gb M-die | |||
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16GB, 2Gx72 Module(2Rank of x4) - page2
S0_n
S1_n
S2_n
S3_n
BA[N:0]
A[N:0]
RAS_n
CAS_n
WE_n
CKE0
CKE1
ODT0
ODT1
CK0_t
CK0_c
CK1_t
CK1_c
1:2
R
E
G
I
S
T
E
R
/
P
L
L
120 â¦
120 â¦
RS0_n â CS1_n: SDRAMs D[17:9]
RS1_n â CS0_n: SDRAMs D[8:0]
RS2_n â CS1_n: SDRAMs D[35:27]
RS3_n â CS0_n: SDRAMs D[26:18]
RBA[N:0]A â BA[N:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
RBA[N:0]B â BA[N:0]: SDRAMs D[7:4], D[16:13], U[25:22], U[34:31]
RA[N:0]A â A[N:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
RA[N:0]B â A[N:0]: SDRAMs D[7:4], D[16:13], U[25:22], U[34:31]
RRASA_n â RAS_n: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
RRASB_n â RAS_n: SDRAMs D[7:4], D[16:13], U[25:22], U[34:31]
RCASA_n â CAS_n: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
RCASB_n â CAS_n: SDRAMs D[7:4], D[16:13], U[25:22], U[34:31]
RWEA_n â WE_n: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
RWEB_n â WE_n: SDRAMs D[7:4], D[16:13], U[25:22], U[34:31]
RCKE0A â CKE1: SDRAMs D[12:9], D17, D[30:27], D35
RCKE0B â CKE1: SDRAMs D[16:13], D[34:31]
RCKE1A â CKE0: SDRAMs D[3:0], D8, D[21:18], D26
RCKE1B â CKE0: SDRAMs D[7:4], D[25:22]
RODT0A â ODT1: SDRAMs D[12:9], D17
RODT0B â ODT1: SDRAMs D[16:13]
RODT1A â ODT1: SDRAMs D[30:27], D35
RODT1B â ODT1: SDRAMs D[34:31]
PCK0A_t â CK_t: SDRAMs D[3:0], D[12:8], D17
PCK0B_t â CK_t: SDRAMs D[7:4], D[16:13]
PCK1A_t â CK_t: SDRAMs D[21:18], D[30:26], D35
PCK1B_t â CK_t: SDRAMs D[25:22], D[34:31]
PCK0A_c â CK_c: SDRAMs D[3:0], D[12:8], D17
PCK0B_c â CK_c: SDRAMs D[7:4], D[16:13]
PCK1A_c â CK_c: SDRAMs D[21:18], D[30:26], D35
PCK1B_c â CK_c: SDRAMs D[25:22], D[34:31]
PAR_IN
RESET_n
Err_Out_n
RST_n
RESET_n: SDRAMs D[35:0]
Rev. 1.0 / Aug. 2012
18
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