HMT451V7MFR8C Datasheet, PDF (41/67 Pages) Hynix Semiconductor – DDR3 SDRAM VLP Registered DIMM Based on 4Gb M-die

DDR3-1066 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 44.
Speed Bin
CL - nRCD - nRP
Parameter
Symbol
Internal read command
to first data
t_AA
ACT to internal read or
write delay time
t_RCD
DDR3-1066F
7-7-7
min
max
13.125
20
13.125
—
PRE command period
t_RP
13.125
—
ACT to ACT or REF
command period
t_RC
ACT to PRE command
period
t_RAS
CL = 5
CWL = 5
CWL = 6
t_CK(AVG)
t_CK(AVG)
CL = 6
CWL = 5
CWL = 6
t_CK(AVG)
t_CK(AVG)
CL = 7
CWL = 5
CWL = 6
t_CK(AVG)
t_CK(AVG)
CL = 8
CWL = 5
CWL = 6
t_CK(AVG)
t_CK(AVG)
Supported CL Settings
Supported CWL Settings
50.625
—
37.5
2.5
1.875
1.875
9 * tREFI
Reserved
Reserved
Reserved
Reserved
Reserved
6, 7, 8
5, 6
3.3
< 2.5
< 2.5
Unit
Note
ns
ns
ns
ns
ns
ns
1, 2, 3, 4, 6
ns
4
ns
1, 2, 3, 6
ns
1, 2, 3, 4
ns
4
ns
1, 2, 3, 4
ns
4
ns
1, 2, 3
n_CK
n_CK
Rev. 1.0 / Aug. 2012
41