HMT451V7MFR8C Datasheet, PDF (42/67 Pages) Hynix Semiconductor – DDR3 SDRAM VLP Registered DIMM Based on 4Gb M-die

DDR3-1333 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 44.
Speed Bin
CL - nRCD - nRP
Parameter
Symbol
Internal read
command to first data
t_AA
ACT to internal read or
write delay time
t_RCD
PRE command period t_RP
ACT to ACT or REF
command period
t_RC
ACT to PRE command
period
t_RAS
CL = 5
CL = 6
CWL = 5
CWL = 6, 7
CWL = 5
CWL = 6
CWL = 7
CWL = 5
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
CL = 7 CWL = 6 t_CK(AVG)
CWL = 7
CWL = 5
CL = 8 CWL = 6
CWL = 7
CWL = 5, 6
CL = 9 _{CWL = 7}
CWL = 5, 6
CL = 10
CWL = 7
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
t_CK(AVG)
Supported CL Settings
Supported CWL Settings
min
13.75
(13.125)^5,9
13.75
(13.125)^5,9
13.75
(13.125)^5,9
48.75
(48.125)^5,9
DDR3-1333H
9-9-9
max
20
—
—
—
36
9 * tREFI
2.5
1.875
1.875
1.5
1.5
Reserved
Reserved
3.3
Reserved
Reserved
Reserved
< 2.5
(Optional)^5,9
Reserved
Reserved
< 2.5
Reserved
Reserved
<1.875
Reserved
<1.875
(Optional)
6, (7), 8, 9, (10)
5, 6, 7
Unit
Note
ns
ns
ns
ns
ns
ns
1,2, 3,4, 7
ns
4
ns
1, 2, 3, 7
ns
1, 2, 3, 4, 7
ns
4
ns
4
ns
1, 2, 3, 4, 7
ns
1, 2, 3, 4
ns
4
ns
1, 2, 3, 7
ns
1, 2, 3, 4
ns
4
ns
1, 2, 3, 4
ns
4
ns
1, 2, 3
ns
5
n_CK
n_CK
Rev. 1.0 / Aug. 2012
42