HMT451V7MFR8C Datasheet, PDF (16/67 Pages) Hynix Semiconductor – DDR3 SDRAM VLP Registered DIMM Based on 4Gb M-die

8GB, 1Gx72 Module(2Rank of x8) - page2
S0_n
S1_n
S[3:2] NC
BA[N:0]
A[N:0]
RAS_n
CAS_n
WE_n
CKE0
ODT0
RS0A_n → CS0_n: SDRAMs D[3:0], D8
1:2 ^{RS0B_n → CS0_n: SDRAMs D[7:4]}
R
E
G
I
S
RBA[N:0]A → BA[N:0]: SDRAMs D[3:0], D[12:8], D17
RBA[N:0]B → BA[N:0]: SDRAMs D[7:4], D[16:13]
RA[N:0]A → A[N:0]: SDRAMs D[3:0], D[12:8], D17
RA[N:0]B → A[N:0]: SDRAMs D[7:4], D[16:13]
T
RRASA_n → RAS_n: SDRAMs D[3:0], D[12:8], D17
E
R
/
RRASB_n → RAS_n: SDRAMs D[7:4], D[16:13]
RCASA_n → CAS_n: SDRAMs D[3:0], D[12:8], D17
RCASB_n → CAS_n: SDRAMs D[7:4], D[16:13]
RWEA_n → WE_n: SDRAMs D[3:0], D[12:8], D17
P
RWEB_n → WE_n: SDRAMs D[7:4], D[16:13]
L
L
RCKE0A → CKE0: SDRAMs D[3:0], D8
RCKE0B → CKE0: SDRAMs D[7:4]
RODT0A → ODT0: SDRAMs D[3:0], D8
RODT0B → ODT0: SDRAMs D[7:4]
CK0_t
CK0_c
CK1_t
CK1_c
120 Ω
120 Ω
PCK0A_t → CK-t: SDRAMs D[3:0], D8
PCK0B_t → CK_t: SDRAMs D[7:4]
PCK0A_c → CK_c: SDRAMs D[3:0], D8
PCK0B_c → CK_c: SDRAMs D[7:4]
PAR_IN
RESET_n
Err_Out_n
RST_n
RST_n: SDRAMs D[17:0]
Rev. 1.0 / Aug. 2012
16