HMT112V7AFP8C-G7 Datasheet, PDF (7/25 Pages) Hynix Semiconductor – 240pin DDR3 SDRAM VLP Registered DIMM

2.2 Input/Output Functional Description
Symbol
CK0
CK0
CK1
CK1
CKE0–CKE1
S0–S3
RAS, CAS, WE
ODT0–ODT1
VREFDQ
VREFCA
VDDQ
BA0–BA2
A0-A9
A10/AP
A11
A12/BC
A13-A15
DQ0–DQ63,
CB0–CB7
Type Polarity
Function
IN
Positive Line
Positive line of the differential pair of system clock inputs that drives input
to the on-DIMM Clock Driver.
IN
Negative Line
Negative line of the differential pair of system clock inputs
input to the on-DIMM Clock Driver.
that drives the
IN Positive Line Terminated but not used on RDIMMs
IN Negative Line Terminated but not used on RDIMMs
CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
IN
Active High
device input buffers and output drivers of the SDRAMs. Taking CKE LOW
provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all
banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank)
Enables the command decoders for the associated rank of SDRAM when
low and disables decoders.When decoders are disabled, new commands
are ignored and previous operations continue.Other combinations of these
IN
Active Low
input signals perform unique functions, including disabling all outputs
(except CKE and ODT) of the register(s) on the DIMM or accessing internal
control words in the register device(s).For modules with two regis-
ters,S[3:2] operate similarly to S[1:0] for the second set of register out-
puts or register control words.
IN
Active Low
When sampled at the positive rising edge of the clock, CAS, RAS, and WE
define the operation to be executed by the SDRAM.
IN Active High On-Die Termination control signals
Supply
Reference voltage for DQ0-DQ63 and CB0-CB7
Supply
Reference voltage for A0-A15, BA0-BA2, RAS, CAS, WE, S0, S1, CKE0,
CKE1, Par_In, ODT0 and ODT1.
Supply
Power supply for the DDR3 SDRAM output buffers to provide improved
noise immunity. For all current DDR3 unbuffered DIMM designs, VDDQ
shares the same power plane as VDD pins.
Selects which SDRAM bank of eight is activated.
IN
—
BA0-BA2 define to which bank an Active, Read, Write or Precharge com-
mand is being applied.Bank address also determines mode register is to be
accessed during an MRS cycle.
Provided the row address for Active commands and the column address
and Auto Precharge bit for Read/Write commands to select one location
out of the memory array in the respective bank.A10 is sampled during a
IN
—
Precharge command to determine whether the Precharge applies to one
bank (A10 LOW) or all banks (A10 HIGH).If only one bank is to be pre-
charged, the bank is selected by BA.A12 is also utilized for BL 4/8 identifi-
cation for “BL on the fly” during CAS command. The address inputs also
provide the op-code during Mode Register Set commands.
I/O
—
Data and Check Bit Input/Output pins.
Rev. 0.2 / December 2008
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