HMT112V7AFP8C-G7 Datasheet, PDF (11/25 Pages) Hynix Semiconductor – 240pin DDR3 SDRAM VLP Registered DIMM

3. Functional Block Diagram
3.1 1GB, 128Mx72 Module(1Rank of x8)
DQS8_t
DQS_t
ZQ
DQS4_t
DQS_t
ZQ
DQS8_c
DQS_c
DQS4_c
DQS_c
DM8/DQS17_t
DQS17_c
TDQS_t
TDQS_c
D8
DM4/DQS13_t
DQS13_c
TDQS_t
TDQS_c
D4
CB[7:0]
DQ [7:0]
DQ[39:32]
DQ [7:0]
DQS3_t
DQS_t
ZQ
DQS5_t
DQS_t
ZQ
DQS3_c
DQS_c
DQS5_c
DQS_c
DM3/DQS12_t
DQS12_c
TDQS_t
TDQS_c
D3
DM5/DQS14_t
DQS14_c
TDQS_t
TDQS_c
D5
DQ[31:24]
DQ [7:0]
DQ[47:40]
DQ [7:0]
DQS2_t
DQS_t
ZQ
DQS6_t
DQS_t
ZQ
DQS2_c
DQS_c
DQS6_c
DQS_c
DM2/DQS11_t
DQS11_c
TDQS_t
TDQS_c
D2
DM6/DQS15-t
DQS15_c
TDQS_t
TDQS_c
D6
DQ[23:16]
DQ [7:0]
DQ[55:48]
DQ [7:0]
DQS1_t
DQS1_c
DM1/DQS10_t
DQS10_c
DQ[15:8]
DQS_t
DQS_c
TDQS_t
TDQS_c
DQ [7:0]
D1
DQS_t
DQS_c
DM/DQS9_t
DQS9_c
DQ[7:0]
DQS_t
DQS_c
TDQS_t
TDQS_c
DQ [7:0]
D0
Vtt
ZQ
DQS7_t
DQS_t
DQS7_c
DQS_c
DM7/DQS16_t
DQS16_c
TDQS_t
TDQS_c
D7
DQ[63:56]
DQ [7:0]
ZQ
Vtt
ZQ
V_DDSPD
VDD
V_TT
VREFCA
VREFDQ
VSS
SPD
D0–D8
D0–D8
D0–D8
D0–D8
Note:
1.DQ-to-I/O wiring may be changed within byte.
2.ZQ resistors are ʃ ‚ 1%.For all other resistor values refer to the
appropriate wiring diagram.
S0_n
S1_n
BA[N:0]
A[N:0]
RAS_n
CAS_n
WE_n
CKE0
ODT0
CK0_t
CK0_c
CK1_t
CK1_c
1:
2
R
E
G
I
S
T
E
R
/
P
120ʃ
‚ 1%
L
L
120ʃ
‚ 1%
RS0A_n ª CS0_n: SDRAMs D[3:0], D8
RS0BCK_n ª CS0_n: SDRAMs D[7:4]
RBA[N:0]A ª BA[N:0]: SDRAMs D[3:0], D8
RBA[N:0]B ª BA[N:0]: SDRAMs D[7:4]
RA[N:0]A ª A[N:0]: SDRAMs D[3:0], D8
RA[N:0]B ª A[N:0]: SDRAMs D[7:4]
RRASA_n ª RAS_n: SDRAMs D[3:0], D8
RRASB_n ª RAS_n: SDRAMs D[7:4]
RCASA_n ª CAS_n: SDRAMs D[3:0], D8
RCASB_n ª CAS_n: SDRAMs D[7:4]
RWEA_n ª WE_n: SDRAMs D[3:0], D8
RWEB_n ª WE_n: SDRAMs D[7:4]
RCKE0A ª CKE0: SDRAMs D[3:0], D8
RCKE0B ª CKE0: SDRAMs D[7:4]
RODT0A ª ODT0: SDRAMs D[3:0], D8
RODT0B ª ODT0: SDRAMs D[7:4]
PCK0A_t ª CK_t: SDRAMs D[3:0], D8
PCK0B_t ª CK_t: SDRAMs D[7:4]
PCK0A_c ª CK_c: SDRAMs D[3:0], D8
PCK0B_c ª CK_c: SDRAMs D[7:4]
VDDSPD
VDDSPD
SA0
SA0
EVENT
EVENT SPD with SA1
SA1
SCL
SCL ^Integrated SA2
SA2
SDA
SDA
TS
VSS
VSS
Plan to use SPD with Integrated TS of Class B and
might be changed on customer’s requests. For more
details of SPD and Thermal sensor, please contact
local Hynix sales representative
PAR_IN
OERR_n Err_Out_n
RESET_n ^RST_n
RST_n: SDRAMs D[8:0]
S[3:2], CKE1, ODT1, are NC (Unused register inputs ODT1 and CKE1 have a 120...330ʃ
resistor to ground
Rev. 0.2 / December 2008
11