HMT451V7MFR8A Datasheet, PDF (6/67 Pages) Hynix Semiconductor – DDR3L SDRAM VLP Registered DIMM Based on 4Gb M-die

Input/Output Functional Descriptions
Symbol
CK0
CK0
CK1
CK1
CKE[1:0]
Type
IN
IN
IN
IN
IN
Polarity
Function
Positive Positive line of the differential pair of system clock inputs that drives input to the on-
Line
DIMM Clock Driver.
Negative Negative line of the differential pair of system clock inputs that drives the input to the
Line
on-DIMM Clock Driver.
Positive
Line
Terminated but not used on RDIMMs.
Negative
Line
Terminated but not used on RDIMMs.
Active
High
CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input
buffers and output drivers of the SDRAMs. Taking CKE LOW provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN
(row ACTIVE in any bank)
S[3:0]
IN
ODT[1:0]
IN
RAS, CAS, WE
IN
V_REFDQ
V_REFCA
Supply
Supply
BA[2:0]
IN
A[15:13,
12/BC,11,
IN
10/AP,[9:0]
DQ[63:0],
CB[7:0]
DM[8:0]
V_DD, V_SS
V_TT
I/O
IN
Supply
Supply
Active
Low
Active
High
Active
Low
—
—
—
Active
High
Enables the command decoders for the associated rank of SDRAM when low and dis-
ables decoders when high. When decoders are disabled, new commands are ignored
and previous operations continue. Other combinations of these input signals perform
unique functions, including disabling all outputs (except CKE and ODT) of the register(s)
on the DIMM or accessing internal control words in the register device(s). For modules
with two registers, S[3:2] operate similarly to S[1:0] for the second set of register out-
puts or register control words.
On-Die Termination control signals
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
operation to be executed by the SDRAM.
Reference voltage for DQ0-DQ63 and CB0-CB7.
Reference voltage for A0-A15, BA0-BA2, RAS, CAS, WE, S0, S1, CKE0, CKE1, Par_In,
ODT0 and ODT1.
Selects which SDRAM bank of eight is activated.
BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being
applied. Bank address also determines mode register is to be accessed during an MRS
cycle.
Provided the row address for Active commands and the column address
and Auto Precharge bit for Read/Write commands to select one location out of the mem-
ory array in the respective bank. A10 is sampled during a Precharge command to deter-
mine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If
only one bank is to be precharged, the bank is selected by BA. A12 is also utilized for BL
4/8 identification for ‘’BL on the fly’’ during CAS command. The address inputs also pro-
vide the op-code during Mode Register Set commands.
Data and Check Bit Input/Output pins
Masks write data when high, issued concurrently with input data.
Power and ground for the DDR SDRAM input buffers and core logic.
Termination Voltage for Address/Command/Control/Clock nets.
Rev. 1.0 / Aug. 2012
6