HMT451V7MFR8A Datasheet, PDF (4/67 Pages) Hynix Semiconductor – DDR3L SDRAM VLP Registered DIMM Based on 4Gb M-die

Key Parameters
MT/s
Grade
DDR3L-1066
-G7
DDR3L-1333
-H9
tCK
(ns)
1.875
1.5
CAS
Latency
(tCK)
tRCD
(ns)
tRP
(ns)
tRAS
(ns)
tRC
(ns)
CL-tRCD-tRP
7
13.125 13.125 37.5 50.625
7-7-7
9
13.5
13.5
(13.125)* (13.125)*
36
49.5
(49.125)*
9-9-9
*SK hynix DRAM devices support optional downbinning to CL7. SPD setting is programmed to match.
Speed Grade
Grade
CL6
-G7
800
-H9
800
Address Table
CL7
1066
1066
Frequency [MHz]
CL8
1066
1066
CL9
1333
CL10
1333
Remark
Refresh Method
Row Address
Column Address
Bank Address
Page Size
4GB(1Rx8)
8K/64ms
A0-A15
A0-A9
BA0-BA2
1KB
8GB(1Rx4)
8K/64ms
A0-A15
A0-A9, A11
BA0-BA2
1KB
8GB(2Rx8)
8K/64ms
A0-A15
A0-A9
BA0-BA2
1KB
16GB(2Rx4)
8K/64ms
A0-A15
A0-A9, A11
BA0-BA2
1KB
16GB(4Rx8)
8K/64ms
A0-A15
A0-A9
BA0-BA2
1KB
Rev. 1.0 / Aug. 2012
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