HMT451V7MFR8A Datasheet, PDF (50/67 Pages) Hynix Semiconductor – DDR3L SDRAM VLP Registered DIMM Based on 4Gb M-die

Symbol
Operating Burst Read Current
Description
I_DD4R
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8^a); AL: 0; CS: High between RD; Command, Address,
Bank Address Inputs: partially toggling according to Table 7; Data IO: seamless read data burst with different
data between one burst and the next one according to Table 7; DM: stable at 0; Bank Activity: all banks open,
RD commands cycling through banks: 0,0,1,1,2,2,...(see Table 7); Output Buffer and RTT: Enabled in Mode
Registers^b); ODT Signal: stable at 0; Pattern Details: see Table 7.
Operating Burst Write Current
I_DD4W
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8^a); AL: 0; CS: High between WR; Command, Address,
Bank Address Inputs: partially toggling according to Table 8; Data IO: seamless read data burst with different
data between one burst and the next one according to Table 8; DM: stable at 0; Bank Activity: all banks open,
WR commands cycling through banks: 0,0,1,1,2,2,...(see Table 8); Output Buffer and RTT: Enabled in Mode
Registers^b); ODT Signal: stable at HIGH; Pattern Details: see Table 8.
Burst Refresh Current
I_DD5B
CKE: High; External clock: On; tCK, CL, nRFC: see Table 1; BL: 8^a); AL: 0; CS: High between REF; Command,
Address, Bank Address Inputs: partially toggling according to Table 9; Data IO: MID_LEVEL; DM: stable at 0;
Bank Activity: REF command every nREF (see Table 9); Output Buffer and RTT: Enabled in Mode Registers^b);
ODT Signal: stable at 0; Pattern Details: see Table 9.
Self-Refresh Current: Normal Temperature Range
I_DD6
T_CASE: 0 - 85 ^oC; Auto Self-Refresh (ASR): Disabled^d);Self-Refresh Temperature Range (SRT): Normal^e); CKE:
Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8^a); AL: 0; CS, Command, Address, Bank
Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Self-Refresh operation; Output Buffer
and RTT: Enabled in Mode Registers^b); ODT Signal: MID_LEVEL
Self-Refresh Current: Extended Temperature Range (optional)
T_CASE: 0 - 95 ^oC; Auto Self-Refresh (ASR): Disabled^d);Self-Refresh Temperature Range (SRT): Extended^e);
I_{DD6ET CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8}a)_{; AL: 0; CS, Command, Address, Bank}
Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Extended Temperature Self-Refresh
operation; Output Buffer and RTT: Enabled in Mode Registers^b); ODT Signal: MID_LEVEL
Rev. 1.0 / Aug. 2012
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