HMT451V7MFR8A Datasheet, PDF (33/67 Pages) Hynix Semiconductor – DDR3L SDRAM VLP Registered DIMM Based on 4Gb M-die

Slew Rate Definitions for Single-Ended Input Signals
See 7.5 “Address / Command Setup, Hold and Derating” on “DDR3L Device Operation” for single-ended
slew rate definitions for address and command signals.

See 7.6 “Data Setup, Hold and Slew Rate Derating” on “DDR3L Device Operation” for single-ended slew
rate definition for data signals.
Slew Rate Definitions for Differential Input Signals
Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in table
and figure below.
Differential Input Slew Rate Definition
Description
Measured
Min
Max
Defined by
Differential input slew rate for rising edge
(CK-CK and DQS-DQS)
V_ILdiffmax V_IHdiffmin [V_IHdiffmin-V_ILdiffmax] / DeltaTRdiff
Differential input slew rate for falling edge
(CK-CK and DQS-DQS)
V_IHdiffmin
V_ILdiffmax
[V_IHdiffmin-V_ILdiffmax] / DeltaTFdiff
Notes:
The differential signal (i.e. CK-CK and DQS-DQS) must be linear between these thresholds.
Delta
TRdiff
VIHdiffmin
0
Delta
TFdiff
VILdiffmax
Differential Input Slew Rate Definition for DQS, DQS and CK, CK
Rev. 1.0 / Aug. 2012
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