HMT451V7MFR8A Datasheet, PDF (14/67 Pages) Hynix Semiconductor – DDR3L SDRAM VLP Registered DIMM Based on 4Gb M-die

8GB, 1Gx72 Module(1Rank of x4) - page2
S0_n
S1_n
BA[2:0]
A[15:0]
RAS_n
CAS_n
WE_n
CKE[1:0]
ODT[1:0]
RS0A_n → CS0A_n: SDRAMs D[3:0], D8, D[12:9], D17
1:2
R
RS1A_n → CS1A_n: SDRAMs D[21:18], D26, D[30:27], D35
RS0B_n → CS0B_n: SDRAMs D[7:4], D[16:13]
RS1B_n → CS1B_n: SDRAMs D[25:22], D[34:31]
E
G
I
S
RBA[2:0]A → BA[2:0]: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35
RBA[2:0]B → BA[2:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
RA[15:0]A → A[15:0]: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35
RA[15:0]B → A[15:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
T
RRASA_n → RAS_n: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35
E
R
/
RRASB_n → RAS_n: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
RCASA_n → CAS_n: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35
RCASB_n → CAS_n: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
RWEA_n → WE_n: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35
P
RWEB_n → WE_n: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
L
RCKE0A → CKE[1:0]A_n: SDRAMs D[3:0], D8. D[12:9], D17
L
RCKE0B → CKE[1:0]B_n: SDRAMs D[21:18], D26, D[30:27], D35
RODT[1:0]A → ODT0: SDRAMs D[3:0], D8. D[12:9], D17
RODT[1:0]B → ODT0: SDRAMs D[21:18], D26, D[30:27], D35
CK0_t
CK0_c
CK1_t
CK1_c
120 Ω
120 Ω
CK0A_t_R0 → CK-t: SDRAMs D[3:0], D8, D[21:18], D26
CK0B_t_R0 → CK_t: SDRAMs D[7:4], D[25:22]
CK0A_t_R1 → CK-t: SDRAMs D[12:9], D17, D[30:27], D35
CK0B_t_R1 → CK_t: SDRAMs D[16:13], D[34:31]
CK0A_c_R0 → CK_c: SDRAMs D[3:0], D8, D[21:18], D26
CK0B_c_R0 → CK_c: SDRAMs D[7:4], D[25:22]
CK0A_c_R1 → CK_c: SDRAMs D[12:9], D17, D[30:27], D35
CK0B_c_R1 → CK_c: SDRAMs D[16:13], D[34:31]
PAR_IN
Err_Out_n
RESET_n RST_n
RST_n: All SDRAMs
* S[3:2]_n are NC (Note: Otherwise stated differently all resistors values on this base are 22+-5%)
Rev. 1.0 / Aug. 2012
14