GMS82524 Datasheet, PDF (59/93 Pages) Hynix Semiconductor – 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS82512/16/24
HYUNDAI MicroElectronics
16. POWER DOWN OPERATION
GMS825xx has a power-down mode. In power-down
mode, power consumption is reduced considerably that in
battery operation. Battery life can be extended a lot.
16.1 STOP Mode
For applications where power consumption is a critical
factor, device provides reduced power of STOP.
Start The Stop Operation
An instruction that STOP causes to be the last instruction
is executed before going into the STOP mode. In the Stop
mode, the on-chip main-frequency oscillator is stopped.
With the clock frozen, all functions are stopped, but the on-
chip RAM and Control registers are held. The port pins
output the values held by their respective port data register,
the port direction registers. The status of peripherals during
Stop mode is shown below.
Peripheral
CPU
RAM
X_IN PIN
X_OUT PIN
Oscillation
I/O ports
Control Registers
Release method
STOP Mode
All CPU operations are disabled
Retain
Low
High
Stop
Retain
Retain
by RESET, by External interrupt
STOP Mode is entered by STOP instruction.
Note: Since the X_IN pin is connected internally to GND to
avoid current leakage due to the crystal oscillator in STOP
mode, do not use STOP instruction when an external clock
is used as the main system clock.
In the Stop mode of operation, V_DD can be reduced to min-
imize power consumption. Be careful, however, that V_DD
is not reduced before the Stop mode is invoked, and that
V_DD is restored to its normal operating level before the
Stop mode is terminated.
The reset should not be activated before V_DD is restored to
its normal operating level, and must be held active long
enough to allow the oscillator to restart and stabilize.
And after STOP instruction, at least two or more NOP in-
struction should be written as shown in example below.
Example:
LDM
STOP
NOP
NOP
:
CKCTLR,#0000_1110B
The Interval Timer Register CKCTLR should be initial-
ized (0F_H or 0E_H) by software in order that oscillation sta-
bilization time should be longer than 20ms before STOP
mode.
Oscillator
(X_IN pin)
Internal Clock
External Interrupt
BIT Counter n n+1 n+2
Normal Operation
STOP Instruction
Executed
n+3
Stop Operation
01
Clear
FE FF
t_ST > 20ms
by software
012
Normal Operation
Before executing Stop instruction, Basic Interval Timer must be set
properly by software to get stabilization time which is longer than 20ms.
Figure 16-1 STOP Mode Release Timing by External Interrupt
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FEB. 2000 Ver 1.00