GMS82524 Datasheet, PDF (55/93 Pages) Hynix Semiconductor – 8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS82512/16/24
HYUNDAI MicroElectronics
activated mode: rising edge, falling edge, and both edge.
INT0 pin
INT1 pin
INT2 pin
INT3 pin
INT0IF
INT0 INTERRUPT
INT1IF
INT1 INTERRUPT
INT2IF
INT2 INTERRUPT
INT3IF
2 22
IEDS
[0F8H]
INT3 INTERRUPT
2
Edge selection
Register
Figure 14-7 External Interrupt Block Diagram
INT0 ~ INT3 are multiplexed with general I/O ports
(R40~R43). To use as an external interrupt pin, the bit of
R4 port mode register PMR4 should be set to “1” corre-
spondingly.
Example: To use as an INT0 and INT2
:
:
;**** Set port as an input port R40,R42
LDM R4DD,#1111_1010B
;
;**** Set port as an external interrupt port
LDM PMR4,#05H
;
;**** Set Falling-edge Detection
LDM IEDS,#0001_0001B
:
:
:
Response Time
The INT0 ~ INT3 edge are latched into INT1IF ~ INT3IF
at every machine cycle. The values are not actually polled
by the circuitry until the next machine cycle. If a request is
active and conditions are right for it to be acknowledged, a
hardware subroutine call to the requested service routine
will be the next instruction to be executed. The DIV itself
takes twelve cycles. Thus, a minimum of twelve complete
machine cycles elapse between activation of an external
interrupt request and the beginning of execution of the first
instruction of the service routine.
Figure 14-8shows interrupt response timings.
max. 12 f_XIN
8 f_XIN
Interrupt Interrupt
goes latched
active
Interrupt
processing
Interrupt
routine
Figure 14-8 Interrupt Response Timing Diagram
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FEB. 2000 Ver 1.00