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| GMS82524 Datasheet, PDF (58/93 Pages) Hynix Semiconductor – 8-BIT SINGLE-CHIP MICROCONTROLLERS | |||
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HYUNDAI MicroElectronics
GMS82512/16/24
Example: Sets the watchdog timer detection time to 0.5 sec at 4.19MHz
LDM
LDM
LDM
:
Within WDT
:
detection time :
:
LDM
:
Within WDT
detection time
:
:
:
LDM
CKCTLR,#3FH
WDTR,#04FH
WDTR,#04FH
WDTR,#04FH
WDTR,#04FH
;Select 1/2048 clock source, WDTON â 1, Clear Counter
;Clear counter
;Clear counter
;Clear counter
Enable and Disable Watchdog
Watchdog timer is enabled by setting WDTON (bit 5 in
CKCTLR) to â1â. WDTON is initialized to â0â during re-
set and it should be set to â1â to operate after reset is re-
leased.
Example: Enables watchdog timer for Reset
:
LDM CKCTLR,#xx1x_xxxxB;WDTON â 1
:
:
The watchdog timer is disabled by clearing bit 5 (WD-
TON) of CKCTLR. The watchdog timer is halted in STOP
mode and restarts automatically after STOP mode is re-
leased.
Watchdog Timer Interrupt
The watchdog timer can be also used as a simple 6-bit tim-
er by clearing bit5 of CKCTLR to â0â. The interval of
watchdog timer interrupt is decided by Basic Interval Tim-
er. Interval equation is shown as below.
T = WDTR Ã Interval of BIT
The stack pointer (SP) should be initialized before using
the watchdog timer output as an interrupt source.
Example: 6-bit timer interrupt set up.
LDM CKCTLR,#xx0xxxxxB;WDTON â0
LDM WDTR,#7FH ;WDTCL â1
:
Source clock
BIT overflow
Binary-counter 1
WDTR
WDTIF interrupt
WDT reset
2
3
0
1
2
n
3
WDTR â â0100_0011Bâ
3
0
Counter
Clear
Match
Detect
reset
Figure 15-3 Watchdog timer Timing
If the watchdog timer output becomes active, a reset is gen-
erated, which drives the RESET pin low to reset the inter-
nal hardware.
The main clock oscillator also turns on when a watchdog
timer reset is generated in sub clock mode.
FEB. 2000 Ver 1.00
55
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