GMS82524 Datasheet, PDF (50/93 Pages) Hynix Semiconductor – 8-BIT SINGLE-CHIP MICROCONTROLLERS

HYUNDAI MicroElectronics
GMS82512/16/24
14. INTERRUPTS
The GMS825xx interrupt circuits consist of Interrupt en-
able register (IENH, IENL), Interrupt request flags of
IRQH, IRQL, Priority circuit, and Master enable flag (“I”
flag of PSW). Thirteen interrupt sources are provided. The
configuration of interrupt circuit is shown in Figure 14-2.
The External Interrupts INT0 ~ INT3 each can be transi-
tion-activated (1-to-0 or 0-to-1 transition) by selection
IEDS.
The flags that actually generate these interrupts are bit
INT0F, INT1F, INT2F and INT3F in register IRQH. When
an external interrupt is generated, the flag that generated it
is cleared by the hardware when the service routine is vec-
tored to only if the interrupt was transition-activated.
The Timer 0 ~ Timer 3 Interrupts are generated by TxIF
which is set by a match in their respective timer/counter
register. The Basic Interval Timer Interrupt is generated by
BITIF which is set by an overflow in the timer register.
The AD converter Interrupt is generated by ADIF which is
set by finishing the analog to digital conversion.
The Watchdog timer Interrupt is generated by WDTIF
which set by a match in Watchdog timer register.
The Basic Interval Timer Interrupt is generated by BITIF
which are set by a overflow in the timer counter register.
The interrupts are controlled by the interrupt master enable
flag I-flag (bit 2 of PSW on page 16), the interrupt enable
register (IENH, IENL), and the interrupt request flags (in
IRQH and IRQL) except Power-on reset and software
BRK interrupt. Below table shows the Interrupt priority.
Reset/Interrupt
Hardware Reset
External Interrupt 0
External Interrupt 1
External Interrupt 2
External Interrupt 3
Timer/Counter 0
Timer/Counter 1
Timer/Counter 2
Timer/Counter 3
ADC Interrupt
Basic Interval Timer
Watchdog Timer
Symbol
RESET
INT0
INT1
INT2
INT3
Timer 0
Timer 1
Timer 2
Timer 3
ADC
BIT
WDT
Priority
1
2
3
4
5
6
7
8
9
10
11
12
Vector addresses are shown in Figure 8-6 on page 18. In-
terrupt enable registers are shown in Figure 14-3. These
registers are composed of interrupt enable flags of each in-
terrupt source and these flags determines whether an inter-
rupt will be accepted or not. When enable flag is “0”, a
corresponding interrupt source is prohibited. Note that
PSW contains also a master enable bit, I-flag, which dis-
ables all interrupts at once.
R/W R/W R/W R/W
IRQH INT0IF INT1IF ^INT2IF INT3IF
MSB
R/W
T0IF
R/W
T1IF
R/W
T2IF
R/W
T3IF
LSB
ADDRESS: 0F7_H
INITIAL VALUE: 0000 0000_B
Timer/Counter 3 interrupt request flag
Timer/Counter 2 interrupt request flag
Timer/Counter 1 interrupt request flag
Timer/Counter 0 interrupt request flag
External interrupt 3 request flag
External interrupt 3 request flag
External interrupt 3 request flag
External interrupt 3 request flag
R/W R/W R/W
IRQL ADIF WDTIF BITIF -
-
-
-
-
ADDRESS: 0F5_H
INITIAL VALUE: 000- ----_B
MSB
LSB
Basic Interval Timer interrupt request flag
Watchdog timer interrupt request flag
A/D Converter interrupt request flag
Figure 14-1 Interrupt Request Flag
FEB. 2000 Ver 1.00
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