HY57V281620ET Datasheet, PDF (5/13 Pages) Hynix Semiconductor – 128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O

Synchronous DRAM Memory 128Mbit (8Mx16bit)
HY57V281620E(L)T(P) Series
FUNCTIONAL BLOCK DIAGRAM
2Mbit x 4banks x 16 I/O Synchronous DRAM
CLK
CKE
CS
RAS
CAS
WE
U/LDQM
Self refresh
logic & timer
Internal Row
Counter
Row Active
Row
Pre
Decoder
Refresh
Column
Active
Column
Pre
Decoder
2Mx16 BANK 3
2Mx16 BANK 2
2Mx16 BANK 1
2Mx16 BANK 0
Memory
Cell
Array
Y-Decoder
DQ0
DQ15
Bank Select
Column Add
Counter
A0
Address
A1
Register
Burst
Counter
Pipe Line
A11
Mode Register
CAS Latency
Data Out Control
Control
BA1
BA0
Rev. 1.1 / Jan. 2005
5