HY57V281620ET Datasheet, PDF (11/13 Pages) Hynix Semiconductor – 128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O

Synchronous DRAM Memory 128Mbit (8Mx16bit)
HY57V281620E(L)T(P) Series
AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)
Parameter
RAS Cycle Time Operation
RAS Cycle Time Auto Refresh
RAS to CAS Delay
RAS Active Time
RAS Precharge Time
RAS to RAS Bank Active Delay
CAS to CAS Delay
Write Command to
Data-In Delay
Data-in to Precharge Command
Data-In to Active Command
DQM to Data-Out Hi-Z
DQM to Data-In Mask
MRS to New Command
Precharge to Data CAS
Output High-Z
Latency=3
CAS
Latency=2
Power Down Exit Time
Self Refresh Exit Time
Refresh Time
Symbol
5
6
7
H
Unit Note
Min Max Min Max Min Max Min Max
tRC
55 - 60 - 63 - 63 - ns
tRRC
55 - 60 - 63 - 63 - ns
tRCD
15 - 18 - 20 - 20 - ns
tRAS
38.7 100K 42 100K 42 100K 42 120K ns
tRP
15 - 18 - 20 - 20 - ns
tRRD
10 - 12 - 14 - 15 - ns
tCCD
1 - 1 - 1 - 1 - CLK
tWTL
0 - 0 - 0 - 0 - CLK
tDPL
tDAL
tDQZ
tDQM
tMRD
2 - 2 - 2 - 2 - CLK
tDPL + tRP
2 - 2 - 2 - 2 - CLK
0 - 0 - 0 - 0 - CLK
2 - 2 - 2 - 2 - CLK
tPROZ3
3 - 3 - 3 - 3 - CLK
tPROZ2
tDPE
tSRE
tREF
2 - 2 - 2 - 2 - CLK
1 - 1 - 1 - 1 - CLK
1 - 1 - 1 - 1 - CLK 1
- 64 - 64 - 64 - 64 ms
Note: 1. A new command can be given tRRC after self refresh exit.
Rev. 1.1 / Jan. 2005
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