HY57V281620ET Datasheet, PDF (4/13 Pages) Hynix Semiconductor – 128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O

Synchronous DRAM Memory 128Mbit (8Mx16bit)
HY57V281620E(L)T(P) Series
PIN DESCRIPTION
SYMBOL
TYPE
DESCRIPTION
CLK
Clock
The system clock input. All other inputs are registered to the SDRAM
on the rising edge of CLK
CKE
Clock Enable
Controls internal clock signal and when deactivated, the SDRAM will
be one of the states among power down, suspend or self refresh
CS
Chip Select
Enables or disables all inputs except CLK, CKE, UDQM and LDQM
BA0, BA1
Bank Address
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
A0 ~ A11
Address
Row Address: RA0 ~ RA11, Column Address: CA0 ~ CA8
Auto-precharge flag: A10
RAS, CAS, WE
Row Address Strobe,
Column Address Strobe,
Write Enable
RAS, CAS and WE define the operation
Refer function truth table for details
UDQM, LDQM
Data Input/Output Mask
Controls output buffers in read mode and masks input data in write
mode
DQ0 ~ DQ15
Data Input/Output
Multiplexed data input / output pin
VDD/VSS
Power Supply/Ground Power supply for internal circuits and input buffers
VDDQ/VSSQ Data Output Power/Ground Power supply for output buffers
NC
No Connection
No connection
Rev. 1.1 / Jan. 2005
4