HY57V281620ET Datasheet, PDF (10/13 Pages) Hynix Semiconductor – 128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O

Synchronous DRAM Memory 128Mbit (8Mx16bit)
HY57V281620E(L)T(P) Series
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
Parameter
System Clock
Cycle Time
CAS
Latency=3
CAS
Latency=2
Clock High Pulse Width
Clock Low Pulse Width
Access Time
From Clock
CAS
Latency=3
CAS
Latency=2
Data-out Hold Time
Data-Input Setup Time
Data-Input Hold Time
Address Setup Time
Address Hold Time
CKE Setup Time
CKE Hold Time
Command Setup Time
Command Hold Time
CLK to Data Output in Low-Z Time
CLK to
Data Output
in High-Z Time
CAS
Latency=3
CAS
Latency=2
Sym-
bol
5
6
7
H
Unit Note
Min Max Min Max Min Max Min Max
tCK3
5.0
6.0
7.0
7.5
ns
1000
1000
1000
1000
tCK2
10
10
10
10
ns
tCHW 1.75 - 2.0 - 2.0 - 2.5 - ns 1
tCLW 1.75 - 2.0 - 2.0 - 2.5 - ns 1
tAC3
- 4.5 - 5.4 - 5.4 - 5.4 ns
2
tAC2
- 6.0 - 6.0 - 6.0 - 6.0 ns
tOH
tDS
tDH
tAS
tAH
tCKS
tCKH
tCS
tCH
tOLZ
2.0 - 2.0 - 2.5 - 2.5 - ns
1.5 - 1.5 - 1.5 - 1.5 - ns 1
0.8 - 0.8 - 0.8 - 0.8 - ns 1
1.5 - 1.5 - 1.5 - 1.5 - ns 1
0.8 - 0.8 - 0.8 - 0.8 - ns 1
1.5 - 1.5 - 1.5 - 1.5 - ns 1
0.8 - 0.8 - 0.8 - 0.8 - ns 1
1.5 - 1.5 - 1.5 - 1.5 - ns 1
0.8 - 0.8 - 0.8 - 0.8 - ns 1
1.0 - 1.0 - 1.5 - 1.5 - ns
tOHZ3 - 4.5 - 5.4 - 5.4 - 5.4 ns
tOHZ2 - 6.0 - 6.0 - 6.0 - 6.0 ns
Note:
1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter.
2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If tR > 1ns,
then (tR/2-0.5)ns should be added to the parameter.
Rev. 1.1 / Jan. 2005
10