HY29F080 Datasheet, PDF (4/38 Pages) Hynix Semiconductor – 8 Megabit (1M x 8), 5 Volt-only, Flash Memory

HY29F080
CONVENTIONS
Unless otherwise noted, a positive logic (active
High) convention is assumed throughout this docu-
ment, whereby the presence at a pin of a higher,
more positive voltage (nominally 5VDC) causes
assertion of the signal. A ‘#’ symbol following the
signal name, e.g., RESET#, indicates that the sig-
nal is asserted in a Low state (nominally 0 volts).
Whenever a signal is separated into numbered
bits, e.g., DQ[7], DQ[6], ..., DQ[0], the family of
bits may also be shown collectively, e.g., as
DQ[7:0].
The designation 0xNNNN (N = 0, 1, 2, . . . , 9, A, .
. . , E, F) indicates a number expressed in hexa-
decimal notation. The designation 0bXXXX indi-
cates a number expressed in binary notation (X =
0, 1).
SIGNAL DESCRIPTIONS
Name
Type
Des c r ip t io n
A[19:0]
Inputs
Address, active High. These twenty inputs select one of 1,048,576 (1M) bytes
within the array for read or write operations. A[19] is the MSB and A[0] is the
LSB.
DQ[7:0]
Inputs/Outputs Data Bus, active High. These pins provide an 8-bit data path for read and write
Tri-state operations.
Chip Enable, active Low. This input must be asserted to read data from or
CE#
Input
write data to the HY29F080. When High, the data bus is tri-stated and the device
is placed in the Standby mode.
OE#
Input
Output Enable, active Low. This input must be asserted for read operations
and negated for write operations. When High, data outputs from the device are
disabled and the data bus pins are placed in the high impedance state.
WE#
Input
Wr it e Enable, act ive Low. Controls writing of commands or command
sequences in order to program data or erase sectors of the memory array. A
write operation takes place when WE# is asserted while CE# is Low and OE#
is High.
RESET#
Input
Hardware Reset, active Low. Provides a hardware method of resetting the
HY29F080 to the read array state. When the device is reset, it immediately
terminates any operation in progress. The data bus is tri-stated and all read/write
commands are ignored while the input is asserted. While RESET# is asserted,
the device will be in the Standby mode.
RY/BY#
Output
Open Drain
Ready/Busy St at us. Indicates whether a write or erase command is in
progress or has been completed. RY/BY# is valid after the rising edge of the
final WE# pulse of a command sequence. It remains Low while the device is
actively programming data or erasing, and goes High when it is ready to read
array data.
V_CC
--
5-volt power supply.
V_SS
--
Power and signal ground.
MEMORY ARRAY ORGANIZATION
The 1 MByte Flash memory array is organized into
sixteen 64 KByte blocks called sectors (S0, S1, . .
. , S15). A sector is the smallest unit that can be
erased. Adjacent pairs of sectors (S0/S1, S2/S3,
. . . , S14/S15) are designated as a sector group.
A sector group is the smallest unit which can be
protected to prevent accidental or unauthorized
erasure. See ‘Bus Operations’ and ‘Command
Definitions’ sections of this document for additional
information on these functions.
Table 1 defines the sector addresses, sector group
addresses and corresponding address ranges for
the HY29F080.
4
Rev. 6.1/May 01