HY29F080 Datasheet, PDF (1/38 Pages) Hynix Semiconductor – 8 Megabit (1M x 8), 5 Volt-only, Flash Memory

HY29F080
8 Megabit (1M x 8), 5 Volt-only, Flash Memory
KEY FEATURES
n 5 Volt Read, Program, and Erase
– Minimizes system-level power
requirements
n High Performance
– Access times as fast as 70 ns
n Low Power Consumption
– 15 mA typical active read current
– 30 mA typical program/erase current
– 5 µA maximum CMOS standby current
n Compatible with JEDEC Standards
– Package, pinout and command-set
compatible with the single-supply Flash
device standard
– Provides superior inadvertent write
protection
n Sector Erase Architecture
– Sixteen equal size sectors of 64K bytes
each
– A command can erase any combination of
sectors
– Supports full chip erase
n Erase Suspend/Resume
– Temporarily suspends a sector erase
operation to allow data to be read from, or
programmed into, any sector not being
erased
GENERAL DESCRIPTION
The HY29F080 is an 8 Megabit, 5 volt-only CMOS
Flash memory organized as 1,048,576 (1M) bytes
of eight-bits each. The device is offered in indus-
try-standard 44-pin PSOP and 40-pin TSOP pack-
ages.
The HY29F080 can be programmed and erased
in-system with a single 5-volt V_CC supply. Inter-
nally generated and regulated voltages are pro-
vided for program and erase operations, so that
the device does not require a high voltage power
supply to perform those functions. The device can
also be programmed in standard EPROM pro-
grammers. Access times as fast as 70ns over the
full operating voltage range of 5.0 volts ± 10% are
offered for timing compatibility with the zero wait
state requirements of high speed microprocessors.
n Sector Group Protection
– Sectors may be locked in groups of two to
prevent program or erase operations
within that sector group
n Temporary Sector Unprotect
– Allows changes in locked sectors
(requires high voltage on RESET# pin)
n Internal Erase Algorithm
– Automatically erases a sector, any
combination of sectors, or the entire chip
n Internal Programming Algorithm
– Automatically programs and verifies data
at a specified address
n Fast Program and Erase Times
– Byte programming time: 7 µs typical
– Sector erase time: 1.0 sec typical
– Chip erase time: 16 sec typical
n Data# Polling and Toggle Status Bits
– Provide software confirmation of
completion of program or erase
operations
n Ready/Busy# Pin
– Provides hardware confirmation of
completion of program and erase
operations
n Minimum 100,000 Program/Erase Cycles
n Space Efficient Packaging
– Available in industry-standard 40-pin
TSOP and 44-pin PSOP packages
LOGIC DIAGRAM
20
A[19:0]
RESET#
CE#
OE#
WE#
8
DQ[7:0]
RY/BY#
Revision 6.1, May 2001