HY5PS12421F-E3 Datasheet, PDF(31/35 Page) Hynix Semiconductor

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HY5PS12421F-E3 Datasheet, PDF (31/35 Pages) Hynix Semiconductor – 512Mb DDR2 SDRAM

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9. tIS and tIH (input setup and hold) derating

1HY5PS12421(L)F

HY5PS12821(L)F

HY5PS121621(L)F

tIS, tIH Derating Values

CK, CK Differential Slew Rate

2.0 V/ns

1.5 V/ns

1.0 V/ns

4.0

3.5

3.0

2.5

2.0

1.5

1.0

Command / 0.9

Address 0.8

Slew 0.7

rate(V/ns) 0.6

0.5

0.4

0.3

0.25

0.2

0.15

0.1

â³tIS

+187

+179

+167

+150

+125

+83

-11

-25

-43

-67

-100

-150

-223

-250

-500

-750

-1250

â³tIH

+94

+89

+83

+75

+45

+21

-14

-31

-54

-83

-125

-188

-292

-375

-500

-708

-1125

â³tIS

TBD

â³tIH

TBD

â³tIS

TBD

â³tIH

TBD

Un i ts

Note s

1) For all input signals the total tIS(setup time) and tIH(hold) time) required is calculated by adding the datasheet value

to the derating value listed in above Table.

Setup(tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and

the first crossing of VIH(ac)min. Setup(tIS) nominal slew rate for a falling signal is defined as the slew rate between the

last crossing of VREF(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the nominal

slew rate for line between shaded âVREF(dc) to ac regionâ, use nominal slew rate for derating value(see fig a.) If the

actual signal is later than the nominal slew rate line anywhere between shaded âVREF(dc) to ac regionâ, the slew rate of

a tangent line to the actual signal from the ac level to dc level is used for derating value(see Fig b.)

Hold(tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and

the first crossing of VREF(dc). Hold(tIH) nominal slew rate for a falling signal is defined as the slew rate between the

last crossing of VREF(dc). If the actual signal is always later than the nominal slew rate line between shaded âdc to

VREF(dc) regionâ, use nominal slew rate for derating value(see Fig.c) If the actual signal is earlier than the nominal slew

rate line anywhere between shaded âdc to VREF(dc) regionâ, the slew rate of a tangent line to the actual signal from the

dc level to VREF(dc) level is used for derating value(see Fig d.)

Although for slow rates the total setup time might be negative(i.e. a valid input signal will not have reached VIH/IL(ac) at

the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac).

For slew rates in between the values listed in table, the derating values may obtained by linear interpolation.

These values are typically not subject to production test. They are verified by design and characterization.

Rev. 1.4 / July 2006

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