HY5PS12421F-E3 Datasheet, PDF (17/35 Pages) Hynix Semiconductor – 512Mb DDR2 SDRAM

1HY5PS12421(L)F
HY5PS12821(L)F
HY5PS121621(L)F
IDD Test Conditions
(IDD values are for full operating range of Voltage and Temperature, Notes 1-5)
Symbol
Conditions
Units
IDD0
Operating one bank active-precharge current; ^tCK = ^{tCK(IDD), tRC} = ^{tRC(IDD), tRAS} = ^tRAS min(IDD) ;
CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are SWITCHING;Data bus inputs are mA
SWITCHING
Operating one bank active-read-precharge current ; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0;
IDD1
tCK ₌ tCK(IDD), tRC ₌ tRC _(IDD), tRAS ₌ tRASmin(IDD), tRCD ₌ tRCD(IDD) _{; CKE is HIGH, CS is HIGH}
mA
between valid commands ; Address bus inputs are SWITCHING ; Data pattern is same as IDD4W
IDD2P
Precharge power-down current ; All banks idle ; tCK = ^tCK(IDD) ; CKE is LOW ; Other control and address
mA
bus inputs are STABLE; Data bus inputs are FLOATING
IDD2Q
Precharge quiet standby current;All banks idle; ^tCK = ^tCK(IDD);CKE is HIGH, CS is HIGH; Other control and _mA
address bus inputs are STABLE; Data bus inputs are FLOATING
IDD2N
Precharge standby current; All banks idle; ^tCK = ^tCK(IDD); CKE is HIGH, CS is HIGH; Other control and
mA
address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Active power-down current; All banks open; ^tCK = ^tCK(IDD); CKE is
Fast PDN Exit MRS(12) = 0
mA
IDD3P
LOW; Other control and address bus inputs are STABLE; Data bus inputs
are FLOATING
Slow PDN Exit MRS(12) = 1
mA
IDD3N
Active standby current; All banks open; ^tCK = ^{tCK(IDD), tRAS} = ^{tRASmax(IDD), tRP} =tRP(IDD); CKE is
HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus mA
inputs are SWITCHING
Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; ^tCK =
IDD4W tCK(IDD), tRAS ₌ tRASmax(IDD), tRP ₌ tRP(IDD); _{CKE is HIGH, CS is HIGH between valid commands;}
mA
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
IDD4R
Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL
= 0; ^tCK = ^{tCK(IDD), tRAS} = ^{tRASmax(IDD), tRP} = ^tRP(IDD); CKE is HIGH, CS is HIGH between valid com-
mA
mands; Address bus inputs are SWITCHING;; Data pattern is same as IDD4W
Burst refresh current; ^tCK = ^tCK(IDD); Refresh command at every ^tRFC(IDD) interval; CKE is HIGH, CS is
IDD5B
HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
mA
SWITCHING
IDD6
Self refresh current; CK and CK at 0V; CKE ≤ 0.2V; Other control and address bus inputs are FLOATING; Data
bus inputs are FLOATING
mA
IDD7
Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL =
tRCD(IDD)-1*tCK(IDD); tCK ₌ tCK(IDD), tRC ₌ tRC(IDD), tRRD ₌ tRRD(IDD), tRCD _{= 1*tCK(IDD); CKE is}
mA
HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pat-
tern is same as IDD4R; - Refer to the following page for detailed timing conditions
Note:
1. IDD specifications are tested after the device is properly initialized
2. Input slew rate is specified by AC Parametric Test Condition
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with all combina-
tions of EMRS bits 10 and 11.
5. Definitions for IDD
LOW is defined as Vin ≤ VILAC(max)
HIGH is defined as Vin ≥ VIHAC(min)
STABLE is defined as inputs stable at a HIGH or LOW level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as:
inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals, and
inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes.
Rev. 1.4 / July 2006
17