HY5PS12421F-E3 Datasheet, PDF (27/35 Pages) Hynix Semiconductor – 512Mb DDR2 SDRAM

1HY5PS12421(L)F
HY5PS12821(L)F
HY5PS121621(L)F
Although for slow slew rates the total setup time might be negative(i.e. a valid input signal will not have reached VIH/IL(ac) at the time
of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac).
For slew rate in between the values listed in table x, the derating valued may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
Fig. a Illustration of nominal slew rate for tIS,tDS
CK,DQS
CK, DQS
V_DDQ
t_IS,
t_IH,
t_DS
t_DH
t_IS,
t_IH,
t_DS
t_DH
V_IH(ac)min
V_IH(dc)min
V_REF(dc)
V_IL(dc)max
V_IL(ac)max
Vss
nominal
slew rate
nominal
slew rate
V_REF to ac
region
Delta TF
Delta TR
Setup Slew Rate
Falling Signal
=
VREF(dc)-V_IL(ac)max
Delta TF
Setup Slew Rate
Rising Signal
=
V_IH(ac)min-VREF(dc)
Delta TR
Rev. 1.4 / July 2006
27