HY5PS12421F-E3 Datasheet, PDF (22/35 Pages) Hynix Semiconductor – 512Mb DDR2 SDRAM

1HY5PS12421(L)F
HY5PS12821(L)F
HY5PS121621(L)F
Parameter
Symbol
DDR2-667
min
max
DQ output access time from CK/CK
tAC
-450
+450
DQS output access time from CK/CK
tDQSCK
-400
+400
CK high-level width
tCH
0.45
0.55
CK low-level width
tCL
0.45
0.55
CK half period
tHP
min(tCL,
tCH)
-
Clock cycle time, CL=x
tCK
3000
8000
DQ and DM input setup time
tDS
50
-
DQ and DM input hold time
tDH
175
-
Control & Address input pulse width for each input
tIPW
0.6
-
DQ and DM input pulse width for each input
tDIPW
0.35
-
Data-out high-impedance time from CK/CK
tHZ
-
tAC max
DQS low-impedance time from CK/CK
tLZ
(DQS)
tAC min
tAC max
DQ low-impedance time from CK/CK
tLZ
(DQ)
2*tAC min
tAC max
DQS-DQ skew for DQS and associated DQ signals
tDQSQ
-
240
DQ hold skew factor
tQHS
-
340
DQ/DQS output hold time from DQS
tQH
tHP - tQHS
-
Write command to first DQS latching transition
tDQSS
WL - 0.25
WL + 0.25
DQS input high pulse width
tDQSH
0.35
-
DQS input low pulse width
tDQSL
0.35
-
DQS falling edge to CK setup time
tDSS
0.2
-
DQS falling edge hold time from CK
tDSH
0.2
-
Mode register set command cycle time
tMRD
2
-
Write postamble
tWPST
0.4
0.6
Write preamble
tWPRE
0.35
-
* _A: _dt_dR_reA_sS_s (_am_ndin_c)_on,_trt_oR_{l i}C_np(_um_t i_sn_e)_tus_pp_tie_mc_eification for DDR2-400 4-4-4_tIi_Ss 45ns, 60ns resp₁e₅c₀tively.
-
Address and control input hold time
tIH
275
-
Read preamble
tRPRE
0.9
1.1
Read postamble
tRPST
0.4
0.6
Activate to precharge command
tRAS
45
70000
Active to active command period for 1KB page size products
tRRD
7.5
-
Active to active command period for 2KB page size products
tRRD
10
-
Four Active Window for 1KB page size products
tFAW
37.5
-
Unit
Note
ps
ps
tCK
tCK
ps
11,12
ps
15
ps
6,7,8,20
ps
6,7,8,21
tCK
tCK
ps
18
ps
18
ps
18
ps
13
ps
12
ps
tCK
tCK
tCK
tCK
tCK
tCK
tCK
10
tCK
ps
5,7,9,22
ps
5,7,9,23
tCK
19
tCK
19
ns
3
ns
4
ns
4
ns
Rev. 1.4 / July 2006
22