HY5PS12421F-E3 Datasheet, PDF (10/35 Pages) Hynix Semiconductor – 512Mb DDR2 SDRAM

1HY5PS12421(L)F
HY5PS12821(L)F
HY5PS121621(L)F
2. Maximum DC Ratings
2.1 Absolute Maximum DC Ratings
Symbol
VDD
VDDQ
VDDL
V_IN, V_OUT
T_STG
Parameter
Voltage on VDD pin relative to Vss
Voltage on VDDQ pin relative to Vss
Voltage on VDDL pin relative to Vss
Voltage on any pin relative to Vss
Storage Temperature
Rating
- 1.0 V ~ 2.3 V
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
-55 to +100
Units
V
V
V
V
°C
Notes
1
1
1
1
1, 2
1. . Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reli-
ability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions.
Please refer to JESD51-2 standard.
2.2 Operating Temperature Condition
Symbol
Toper
Parameter
Operating Temperature
Rating
0 to 85
Units
°C
Notes
1,2
1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions,
please refer to JESD51-2 standard.
2. The operating temperature range are the temperature where all DRAM specification will be supported. Outside of this temperature
rang, even it is still within the limit of stress condition, some deviation on portion of operation specification may be required. During
operation, the DRAM case temperature must be maintained between 0 ~ 85°C under all other specification parameters. However,
in some applications, it is desirable to operate the DRAM up to 95°C case temperature. Therefore 2 spec options may exist.
1) Supporting 0 - 85°C with full JEDEC AC & DC specifications. This is the minimum requirements for all operating tempera-
ture options.
2) Supporting 0 - 85°C and being able to extend to 95°C with doubling auto-refresh commands in frequency to a 32 ms
period(tRFI=3.9us).
Note; Currently the periodic Self-Refresh interval is hard coded within the DRAM to a specific value.
There is a migration plan to support higher temperature Self-Refresh entry via the control of EMRS(2) bit A7. However, since
Self-Refresh control function is a migrated process. For our DDR2 module user, it is imperative to check SPD Byte 49 Bit 0
to ensure the DRAM parts support higher than 85°C case temperature Self-Refresh entry.
1) if SPD Byte 49 Bit 0 is a “0” means DRAM does not support Self-Refresh at higher than 85°C, then system have to ensure
the DRAM is at or below 85°C case temperature before initiating Self-Refresh operation.
2) if SPD Byte 49 Bit 0 is a “1” means DRAM supports Self-Refresh at higher than 85°C case temperature, then system can
use register bit A7 at EMRS(2) control DRAM to operate at proper Self-Refresh rate for higher temperature. Please also
refer to EMRS(2) register definition section and DDR2 DIMM SPD definition for details.
Rev. 1.4 / July 2006
10