HMT312S6BFR6C-G7 Datasheet, PDF (24/54 Pages) Hynix Semiconductor – 204pin DDR3 SDRAM SODIMM

Single Ended Output Slew Rate
When the Reference load for timing measurements, output slew rate for falling and rising edges is defined
and measured between V_OL(AC) and V_OH(AC) for single ended signals are shown in table and figure below.
Single-ended Output slew Rate Definition
Description
Measured
From
To
Defined by
Single-ended output slew rate for rising edge
Single-ended output slew rate for falling edge
V_OL(AC)
V_OH(AC)
V_OH(AC)
V_OL(AC)
[V_OH(AC)-V_OL(AC)] / DeltaTRse
[V_OH(AC)-V_OL(AC)] / DeltaTFse
Notes:
1. Output slew rate is verified by design and characterisation, and may not be subject to production test.
Delta TRse
vOH(AC)
VÕ
Delta TFse
vOl(AC)
Single Ended Output Slew Rate Definition
Single Ended Output slew Rate Definition
Output Slew Rate (single-ended)
DDR3-800 DDR3-1066
Parameter
Symbol Min Max Min Max
Single-ended Output Slew Rate SRQse 2.5
5
2.5
5
Description: SR; Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
se: Single-ended Signals
For Ron = RZQ/7 setting
DDR3-1333
Min Max
2.5
5
DDR3-1600
Min Max
TBD 5
Units
V/ns
Rev. 0.2 / Feb. 2010
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