HMT312S6BFR6C-G7 Datasheet, PDF (15/54 Pages) Hynix Semiconductor – 204pin DDR3 SDRAM SODIMM

AC and DC Input Levels for Single-Ended Signals
DDR3 SDRAM will support two Vih/Vil AC levels for DDR3-800 and DDR3-1066 as specified in the table
below. DDR3 SDRAM will also support corresponding tDS values (Table 41 and Table 47 in “ DDR3 Device
Operation”) as well as derating tables in Table 44 of “DDR3 Device Operation” depending on Vih/Vil AC lev-
els.
Single Ended AC and DC Input Levels for DQ and DM
Symbol
Parameter
DDR3-800/1066
Min
Max
DDR3-1333/1600
Min
Max
Unit Notes
VIH.CA(DC100)
VIL.CA(DC100)
VIH.CA(AC175)
VIL.CA(AC175)
VIH.CA(AC150)
VIL.CA(AC150)
DC input logic high
DC input logic low
AC input logic high
AC input logic low
AC Input logic high
AC input logic low
Vref + 0.100
VDD
Vref + 0.100
VDD
V1
VSS
Vref - 0.100
VSS
Vref - 0.100 V
1
Vref + 0.175
Note2
-
-
V 1, 2
Note2
Vref - 0.175
-
-
V 1, 2
Vref + 0.150
Note2
Vref + 0.150
Note2
V 1, 2
Note2
Vref - 0.150
Note2
Vref - 0.150 V 1, 2
V_RefDQ(DC)
Reference Voltage for DQ,
DM inputs
0.49 * VDD
0.51 * VDD
0.49 * VDD
0.51 * VDD
V 3, 4
Notes:
1. Vref = VrefDQ (DC).
2. Refer to “Overshoot and Undershoot Specifications” on page 27.
3. The ac peak noise on V_Ref may not allow V_Ref to deviate from V_RefDQ(DC) by more than +/-1% VDD (for
reference: approx. +/- 15 mV).
4. For reference: approx. VDD/2 +/- 15 mV.
Rev. 0.2 / Feb. 2010
15