HY29F002T Datasheet, PDF (2/38 Pages) Hynix Semiconductor – 2 Megabit (256K x 8), 5 Volt-only, Flash Memory

HY29F002T
HY29F002T has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.
The device is compatible with the JEDEC single
power-supply Flash command set standard. Com-
mands are written to the command register using
standard microprocessor write timings, from where
they are routed to an internal state-machine that
controls the erase and programming circuits.
Device programming is performed a byte at a time
by executing the four-cycle Program Command.
This initiates an internal algorithm that automati-
cally times the program pulse widths and verifies
proper cell margin.
The HY29F002T’s sector erase architecture allows
any number of array sectors to be erased and re-
programmed without affecting the data contents
of other sectors. Device erasure is initiated by
executing the Erase Command. This initiates an
internal algorithm that automatically preprograms
the array (if it is not already programmed) before
executing the erase operation. During erase
cycles, the device automatically times the erase
pulse widths and verifies proper cell margin.
To protect data in the device from accidental or
unauthorized attempts to program or erase the
device while it is in the system (e.g., by a virus),
BLOCK DIAGRAM
the device has a Sector Protect function which
hardware write protects selected sectors. The
sector protect and unprotect features can be en-
abled in a PROM programmer. Temporary Sec-
tor Unprotect, which requires a high voltage, al-
lows in-system erasure and code changes in pre-
viously protected sectors.
Erase Suspend enables the user to put erase on
hold for any period of time to read data from, or
program data to, any sector that is not selected
for erasure. True background erase can thus be
achieved. The device is fully erased when shipped
from the factory.
Addresses and data needed for the programming
and erase operations are internally latched during
write cycles, and the host system can detect
completion of a program or erase operation by
reading the DQ[7] (Data# Polling) and DQ[6]
(toggle) status bits. Reading data from the device
is similar to reading from SRAM or EPROM de-
vices. Hardware data protection measures include
a low V_CC detector that automatically inhibits write
operations during power transitions.
The host can place the device into the standby
mode. Power consumption is greatly reduced in
this mode.
DQ[7:0]
DQ[7:0]
WE#
CE#
OE#
RESET#
STATE
CONTROL
COMMAND
REGISTER
ELECTRONIC
ID
V_SS
V_CC
A[17:0]
V_CC DETECTOR
ERASE VOLTAGE
GENERATOR AND
SECTOR SWITCHES
I/O CONTROL
PROGRAM
VOLTAGE
GENERATOR
Y-DECODER
TIMER
X-DECODER
I/O BUFFERS
DATA LATCH
Y-GATING
2 MBIT
FLASH
MEMORY
ARRAY
(7 Sectors)
2
Rev. 4.1/May 01