HY29F002T Datasheet, PDF (1/38 Pages) Hynix Semiconductor – 2 Megabit (256K x 8), 5 Volt-only, Flash Memory

HY29F002T
2 Megabit (256K x 8), 5 Volt-only, Flash Memory
KEY FEATURES
n 5 Volt Read, Program, and Erase
– Minimizes system-level power requirements
n High Performance
– Access times as fast as 45 ns
n Low Power Consumption
– 20 mA typical active read current
– 30 mA typical program/erase current
– 1 µA typical CMOS standby current
n Compatible with JEDEC Standards
– Package, pinout and command-set
compatible with the single-supply Flash
device standard
– Provides superior inadvertent write
protection
n Sector Erase Architecture
– Boot sector architecture with top boot
block location
– One 16 Kbyte, two 8 Kbyte, one 32 Kbyte
and three 64K byte sectors
– A command can erase any combination of
sectors
– Supports full chip erase
n Erase Suspend/Resume
– Temporarily suspends a sector erase
operation to allow data to be read from, or
programmed into, any sector not being
erased
GENERAL DESCRIPTION
The HY29F002T is an 2 Megabit, 5 volt-only
CMOS Flash memory organized as 262,144
(256K) bytes. The device is offered in industry-
standard 32-pin TSOP and PLCC packages.
The HY29F002T can be programmed and erased
in-system with a single 5-volt V_CC supply. Inter-
nally generated and regulated voltages are pro-
vided for program and erase operations, so that
the device does not require a high voltage power
supply to perform those functions. The device can
also be programmed in standard EPROM pro-
grammers. Access times as fast as 55ns over the
full operating voltage range of 5.0 volts ± 10% are
offered for timing compatibility with the zero wait
state requirements of high speed microprocessors.
A 45ns version operating over 5.0 volts ± 5% is
also available. To eliminate bus contention, the
n Sector Protection
– Any combination of sectors may be
locked to prevent program or erase
operations within those sectors
n Temporary Sector Unprotect
– Allows changes in locked sectors
(requires high voltage on RESET# pin)
n Internal Erase Algorithm
– Automatically erases a sector, any
combination of sectors, or the entire chip
n Internal Programming Algorithm
– Automatically programs and verifies data
at a specified address
n Fast Program and Erase Times
– Byte programming time: 7 µs typical
– Sector erase time: 1.0 sec typical
– Chip erase time: 7 sec typical
n Data# Polling and Toggle Status Bits
– Provide software confirmation of
completion of program or erase
operations
n Minimum 100,000 Program/Erase Cycles
n Space Efficient Packaging
– Available in industry-standard 32-pin
TSOP and PLCC packages
LOGIC DIAGRAM
18
A[17:0]
RESET#
CE#
OE#
WE#
8
DQ[7:0]
Revision 4.1, May 2001