HY29F002T Datasheet, PDF (13/38 Pages) Hynix Semiconductor – 2 Megabit (256K x 8), 5 Volt-only, Flash Memory

may be loaded in any sequence, and the number
of sectors specified may be from one sector to all
sectors. The only restriction is that the time be-
tween these additional data cycles must be less
than 50 µs, otherwise erasure may begin before
the last data cycle is accepted. To ensure that all
data cycles are accepted, it is recommended that
host processor interrupts be disabled during the
time that the additional cycles are being issued
and then be re-enabled afterwards.
Note: The device is capable of accepting three ways
of invoking Erase Commands for additional sectors
during the time-out window. The preferred method,
described above, is the sector erase data cycle after
the initial six bus cycle command sequence. How-
ever, the device also accepts the following methods
of specifying additional sectors during the sector
erase time-out:
n Repeat the entire six-cycle command sequence, speci-
fying the additional sector in the sixth cycle.
n Repeat the last three cycles of the six-cycle command
sequence, specifying the additional sector in the third
cycle.
If all sectors scheduled for erasing are within pro-
tected sectors, the device returns to reading ar-
ray data after approximately 100 µs. If at least
one selected sector is not protected, the erase
operation erases the unprotected sectors, and ig-
HY29F002T
nores the command for the selected sectors that
are protected.
The system can monitor DQ[3] to determine if the
50 µs sector erase time-out has expired, as de-
scribed in the Write Operation Status section. If
the time between additional sector erase data
cycles can be insured to be less than the time-
out, the system need not monitor DQ[3].
Any command other than Sector Erase or Erase
Suspend during the time-out period resets the
device to reading array data. The system must
then rewrite the command sequence, including any
additional sector erase data cycles. Once the
sector erase operation itself has begun, only the
Erase Suspend command is valid. All other com-
mands are ignored.
As for the Chip Erase command, note that a hard-
ware reset immediately terminates the erase op-
eration. To ensure data integrity, the aborted Sec-
tor Erase command sequence should be reissued
once the reset operation is complete.
When the Automatic Erase algorithm terminates,
the device returns to the Read mode. Several
methods are provided to allow the host to deter-
mine the status of the erase operation, as de-
scribed in the Write Operation Status section.
START
Write First Five Cycles of
SECTOR ERASE
Command Sequence
Setup First (or Next) Sector
Address for Erase Operation
Check Erase Status
(See Write Operation Status
Section)
DQ[5] Error Exit
Normal Exit
ERASE COMPLETE
GO TO
ERROR RECOVERY
Write Last Cycle (SA/0x30)
of SECTOR ERASE
Command Sequence
Erase An
YES
Additional Sector?
NO
Sector Erase
Time-out (DQ[3])
Expired?
YES
NO
Sectors which require erasure
but which were not specified in
this erase cycle must be erased
later using a new command
sequence
Figure 6. Sector Erase Procedure
Rev. 4.1/May 01
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