HY27UH08AG5M Datasheet, PDF (18/49 Pages) Hynix Semiconductor – 16Gbit (2Gx8bit) NAND Flash

HY27UH08AG(5/D)M Series
16Gbit (2Gx8bit) NAND Flash
4. OTHER FEATURES
4.1 Data Protection & Power on/off Sequence
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal
voltage detector disables all functions whenever Vcc is below about 2V(3.3V device). WP pin provides hardware pro-
tection and is recommended to be kept at VIL during power-up and power-down. A recovery time of minimum 10us is
required before internal circuit gets ready for any command sequences as shown in Figure 26. The two-step command
sequence for program/erase provides additional software protection.
4.2 Ready/Busy.
The device has a Ready/Busy output that provides method of indicating the completion of a page program, erase,
copy-back, cache program and random read completion. The R/B pin is normally high and goes to low when the device
is busy (after a reset, read, program, erase operation). It returns to high when the internal controller has finished the
operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up
resistor value is related to tr(R/B) and current drain during busy (Ibusy), an appropriate value can be obtained with
the following reference chart (Fig 27). Its value can be determined by the following guidance.
Rev. 0.6 / Dec. 2006