HY27UH08AG5M Datasheet, PDF (13/49 Pages) Hynix Semiconductor – 16Gbit (2Gx8bit) NAND Flash

HY27UH08AG(5/D)M Series
16Gbit (2Gx8bit) NAND Flash
3. DEVICE OPERATION
3.1 Page Read.
Page read operation is initiated by writing 00h and 30h to the command register along with five address cycles. In two
consecutive read operations, the second one doesn’t’ need 00h command, which five address cycles and 30h com-
mand initiates that operation. Two types of operations are available : random read, serial page read. The random read
mode is enabled when the page address is changed. The 2112 bytes (X8 device) of data within the selected page are
transferred to the data registers in less than 25us(tR, 3.3V device). The system controller may detect the completion
of this data transfer (tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the data registers,
they may be read out in 30ns cycle time by sequentially pulsing RE. The repetitive high to low transitions of the RE
clock make the device output the data starting from the selected column address up to the last column address.
The device may output random data in a page instead of the consecutive sequential data by writing random data out-
put command.
The column address of next data, which is going to be out, may be changed to the address which follows random data
output command.
Random data output can be operated multiple times regardless of how many times it is done in a page.
3.2 Page Program.
The device is programmed basically by page, but it does allow multiple partial page programming of a word or consec-
utive bytes up to 2112 (X8 device) , in a single page program cycle.
The number of consecutive partial page programming operation within the same page without an intervening erase
operation must not exceed 8; for example, 4 times for main array (X8 device:1time/512byte, X16 device:1time
256word) and 4 times for spare array (X8 device:1time/16byte ,X16 device:1time/8word).
The addressing should be done in sequential order in a block. A page program cycle consists of a serial data
loading period in which up to 2112bytes (X8 device) of data may be loaded into the data register, followed by a non-
volatile programming period where the loaded data is programmed into the appropriate cell.
The serial data loading period begins by inputting the Serial Data Input command (80h), followed by the five cycle
address inputs and then serial data. The words other than those to be programmed do not need to be loaded. The
device supports random data input in a page. The column address of next data, which will be entered, may be
changed to the address which follows random data input command (85h). Random data input may be operated multi-
ple times regardless of how many times it is done in a page.
The Page Program confirm command (10h) initiates the programming process. Writing 10h alone without previously
entering the serial data will not initiate the programming process. The internal write state controller automatically exe-
cutes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other
tasks. Once the program process starts, the Read Status Register command may be entered to read the status register.
The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit (I/
O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in
progress. When the Page Program is complete, the Write Status Bit (I/O 0) may be checked. The internal write verify
detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Sta-
tus command mode until another valid command is written to the command register. Figure 14 details the sequence.
Rev. 0.6 / Dec. 2006