HMT425S6MFR6A Datasheet, PDF (10/53 Pages) Hynix Semiconductor – DDR3L SDRAM Unbuffered SODIMMs Based on 4Gb M-die

4GB, 512Mx64 Module(1Rank of x8)
DQS0
DQS0
DM0
DQ[0:7]
DQS2
DQS2
DM2
DQ[16:23]
DQS4
DQS4
DM4
DQ[32:39]
DQS
DQS
DM
DQ [0:7]
240ohm
+/-1%
ZQ
D0
DQS1
DQS1
DM1
DQ[8:15]
DQS
DQS
DM
DQ [0:7]
240ohm
+/-1%
ZQ
D1
DQS3
DQS3
DM3
DQ[24:31]
DQS
DQS
DM
DQ [0:7]
240ohm
+/-1%
ZQ
D2
DQS5
DQS5
DM5
DQ[40:47]
DQS
DQS
DM
DQ [0:7]
240ohm
+/-1%
ZQ
SCL
SA0
SA1
SCL
A0
A1
Temp Sensor
(with SPD)
A2
EVENT
SDA
D4
EVENT
The SPD may be
integrated with the Temp
Sensor or may be
a separate component
SCL
SCL
SA0
SA1
A0
A1
(SPD)
SDA
A2
WP
DQS
DQS
DM
DQ [0:7]
LDQS
LDQS
LDM
DQ [0:7]
240ohm
+/-1%
ZQ
D5
240ohm
+/-1%
ZQ
D6
V_tt
VDDSPD
VREFCA
VREFDQ
VDD
VSS
CK0
CK0
CK1
CK1
S1
ODT1
CKE1
EVENT
RESET
Vtt
SPD/TS
D0–D7
D0–D7
D0–D7
D0–D7, SPD, Temp sensor
D0–D7
D0–D7
Terminated near
card edge
NC
NC
NC
Temp Sensor
D0-D7
V1
D4
V2
D5
V3
V4
D6
D7
DQS3
DQS3
DM3
DQ[48:55]
DQS
DQS
DM
DQ [0:7]
240ohm
+/-1%
ZQ
D3
DQS7
DQS7
DM7
DQ[56:63]
LDQS
LDQS
LDM
DQ [0:7]
240ohm
+/-1%
ZQ
D7
V1
D0
V2
D1
V3
V4
D2
D3
Address and Control Lines
NOTES
1. DQ wiring may differ from that
shown however, DQ, DM, DQS, and
DQS relationships are maintained as
shown
Rank 0
Rev. 1.0 / Jul. 2012
10