HDMP-3268 Datasheet, PDF (3/18 Pages) Agilent(Hewlett-Packard) – 3.2 Gbit/sec 68x68 Crosspoint Switch

High-Speed Inputs and Outputs
Figure 2 shows simplified circuit
diagrams for the HDMP-3268’s
high speed input and output cells.
A typical connection between the
output and input cells is also
shown. The output cell is
designed to drive 50 Ω transmis-
sion lines and to be terminated at
the destination end in 50 Ω.
When the output is intended to
connect to the input of another
HDMP-3268 as in a CLOS
architecture, no AC coupling
capacitors are required. The
output amplitude of the HDMP-
3268 is programmable in three
levels from approximately
500 mV to 1.0 V peak-to-peak
differential. In addition, the
output driver and its associated
multiplexer can be turned off to
save power if an output is not
used.
The HDMP-3268 high speed
input cell provides on-chip
termination resistors of 50 Ω
from each input to an on-chip
bias voltage generator which sets
the input common mode voltage
at approximately 0.7 V below the
positive supply. When the input is
intended to be DC coupled, as in
the case of the input being
connected to the output of
another HDMP-3268, the
common mode bias voltage is
disconnected from the termina-
tion resistors, and the two 50 Ω
resistors form a 100 Ω
differential termination. DC
coupling is the default setting for
the HDMP-3268. The input cell
has levels of input equalization
which can be programmed
through the digital control
interface. The AC termination
voltage also can be enabled
through a control register.
Unused input cells can be
disabled to save power.
Figure 3 shows a typical transfer
characteristic of the high-speed
input for the different input
equalization settings. The correct
equalization setting depends
upon the actual PCB environment
in which the HDMP-3268 resides.
The recommended procedure to
set the input equalization setting
is to characterize the HDMP-3268
on the PCB and to adjust the
equalization setting to give
minimum jitter at the output of
the HDMP-3268. The correct
equalization settings should be
stored and loaded into the
HDMP-3268 upon power-up. The
AC characteristics of the high
speed input, high speed output,
and multiplexer block are
specified in Table 8, AC Electrical
Specifications.
Digital Interface
The HDMP-3268 has a parallel bi-
directional digital interface for
configuring the switch matrix and
for controlling the various
functions such as input
equalization, output amplitude,
and power on/off. All of the
registers can be read back to
check valid programming. There
are 204 7-bit registers organized
into three sets of 68 registers
each. One set is used to control
power on/off, equalization, etc.
The other two sets are used to
configure the switch matrix. The
individual registers are accessed
using an address/data scheme.
The particular register address is
placed on the CH[6:0] lines, and
the register data is placed on the
DATA[6:0] lines, either by the
controller in write mode (RW=0),
or by the HDMP-3268 in read
mode (RW=1). Data is latched
into the internal registers on the
rising edge of WSTB. The control
registers are accessed when the
CNTL signal is high. Otherwise,
the address registers are
accessed. Figure 4 and Table 1
show the register read and write
timing diagram and specifica-
tions. See the switch matrix
configuration section for more
details. A chip select signal allows
HIGH SPEED INPUT
AC TRANSFER CHARACTERISTIC
GAIN_DC
BOOST
3 dB
F_peak F_3dB
FREQUENCY
Figure 3. Typical high-speed input equalization curve.
TYPICAL PERFORMANCE OF HIGH SPEED
INPUT CELL WITH DIFFERENT EQUALIZATION SETTINGS
EQUALIZATION GAIN_DC BOOST F_peak
SETTING
(dB)
(dB)
(GHz)
F_3dB
(GHz)
000
16.0
0
N/A
7.9
001
11.4
3.7
3.4
10.7
010
12.9
4.8
2.7
10.2
011
12.9
5.4
2.3
10.0
100
12.9
5.8
2.0
9.8
101
12.9
6.1
1.8
9.8
110
10.5
6.5
1.8
10.6
111
9.8
7.3
1.8
11.2
THIS DATA IS FOR ILLUSTRATIVE PURPOSES ONLY.
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